Patents by Inventor Takaaki Hioka
Takaaki Hioka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230026157Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type, and a vertical Hall element provided on the semiconductor substrate. The vertical Hall element includes an impurity diffusion layer of a second conductivity type and three or more electrodes. The impurity diffusion layer is provided on the semiconductor substrate and has an impurity concentration which increases as a depth increases. The three or more electrodes are provided in a straight line on a surface of the impurity diffusion layer and are composed of an impurity region of the second conductivity type having a higher concentration than the impurity diffusion layer.Type: ApplicationFiled: March 16, 2022Publication date: January 26, 2023Applicant: ABLIC Inc.Inventor: Takaaki HIOKA
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Patent number: 11536783Abstract: A semiconductor device includes a vertical Hall element provided in a first region of a semiconductor substrate, and having the first to the third electrodes arranged side by side in order along a first straight line; a circuit provided in a second region of the semiconductor substrate different from the first region, and having a heat source; and a second straight line intersecting orthogonally a current path for a Hall element drive current which flows between the first electrode and the third electrode. The second line passes a center of the vertical Hall element, and a center point of a region which reaches the highest temperature in the circuit during an operation of the vertical Hall element lies on the second straight line.Type: GrantFiled: January 23, 2020Date of Patent: December 27, 2022Assignee: ABLIC INC.Inventors: Takaaki Hioka, Tomoki Hikichi
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Patent number: 11099244Abstract: A semiconductor device includes a semiconductor substrate 10 of a first conductivity type, a vertical Hall element 100 provided on the semiconductor substrate 10, and an excitation conductor 200 provided directly above the vertical Hall element 100 with an intermediation of an insulating film 30. The vertical Hall element 100 includes a semiconductor layer 101 of a second conductivity type provided on the semiconductor substrate 10, and a plurality of electrodes 111 through 115 each constituted from a high-concentration second conductivity type impurity region and provided on the surface of the semiconductor layer 101 along a straight line. A ratio WC/WH between a width WC of the excitation conductor 200 and a width WH of each of the plurality of electrodes 111 through 115 satisfies 0.3?WC/WH?1.0.Type: GrantFiled: June 18, 2019Date of Patent: August 24, 2021Assignee: ABLIC INC.Inventors: Takaaki Hioka, Hirotaka Uemura
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Patent number: 11069851Abstract: A semiconductor devices has a vertical Hall element formed on a semiconductor substrate, the vertical Hall element including a semiconductor layer of a second conductivity type formed above the semiconductor substrate; an impurity diffusion layer of the second conductivity type formed in an upper portion of the semiconductor layer and having a concentration higher than that of the semiconductor layer; a plurality of electrodes formed on a surface of the impurity diffusion layer, arrayed in a straight line, and each formed from an impurity region of the second conductivity type; a plurality of electrode isolation diffusion layers of the first conductivity type each formed between two adjacent electrodes; and a buried layer formed between the semiconductor substrate and the semiconductor layer, and having a concentration higher than that of the semiconductor layer and lower than that of the impurity diffusion layer.Type: GrantFiled: October 25, 2019Date of Patent: July 20, 2021Assignee: ABLIC INC.Inventor: Takaaki Hioka
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Patent number: 11016151Abstract: The semiconductor device includes a first vertical Hall element provided in a first region of a semiconductor substrate, and including a first plurality of electrodes arranged at predetermined intervals on a first straight line, a second vertical Hall element provided in a second region of the semiconductor substrate different from the first region, and including a second plurality of electrodes of the same number as that of the first plurality of electrodes, the second plurality of electrodes being arranged at the predetermined intervals on a second straight line parallel to the first straight line, a first drive power source configured to drive the first vertical Hall element, and a second drive power source configured to drive the second vertical Hall element and provided separately from the first drive power source.Type: GrantFiled: March 11, 2019Date of Patent: May 25, 2021Assignee: ABLIC INC.Inventors: Takaaki Hioka, Tomoki Hikichi
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Patent number: 10971678Abstract: A semiconductor device includes a first and a second vertical Hall elements formed parallel to each other. Each of the first and the second vertical Hall elements includes: a semiconductor layer on the semiconductor substrate; a Hall voltage output electrode and a first and a second drive current supply electrodes each formed of an impurity region, and sequentially arranged along a straight line on the semiconductor layer; and a first electrode isolation diffusion layer between the first drive current supply electrode and the Hall voltage output electrode, and a second electrode isolation diffusion layer between the Hall voltage output electrode and the second drive current supply electrode. The first and the second drive current supply electrodes each has the second depth deeper than the first depth of the Hall voltage output electrode and the depth of each of the electrode isolation diffusion layers.Type: GrantFiled: April 22, 2019Date of Patent: April 6, 2021Assignee: ABLIC INC.Inventor: Takaaki Hioka
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Patent number: 10847710Abstract: The semiconductor device includes a vertical Hall element that is provided in a first region of a semiconductor substrate and has a plurality of first electrodes, and a resistive element that is provided in a second region different from the first region in the semiconductor substrate and has a plurality of second electrodes. The plurality of first electrodes and the plurality of second electrodes are connected so that resistances of current paths are substantially the same in any phase in which the vertical Hall element is driven using a spinning current method.Type: GrantFiled: March 25, 2019Date of Patent: November 24, 2020Assignee: ABLIC Inc.Inventors: Takaaki Hioka, Tomoki Hikichi
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Publication number: 20200333820Abstract: A constant current circuit includes a depletion-type NMOS transistor having a drain connected to a constant current output terminal, and a resistance element provided between the depletion-type NMOS transistor and a ground terminal. The depletion-type NMOS transistor includes a first depletion-type NMOS transistor and a second depletion-type NMOS transistor which are connected in parallel and arranged to have current directions forming an angle of 90 degrees. The resistance element includes a first resistor and a second resistor which are arranged to have current directions forming an angle of 90 degrees.Type: ApplicationFiled: April 2, 2020Publication date: October 22, 2020Inventors: Tomoki HIKICHI, Kentaro Fukai, Takaaki Hioka, Yohei Ogawa
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Publication number: 20200249284Abstract: A semiconductor device includes a vertical Hall element provided in a first region of a semiconductor substrate, and having the first to the third electrodes arranged side by side in order along a first straight line; a circuit provided in a second region of the semiconductor substrate different from the first region, and having a heat source; and a second straight line intersecting orthogonally a current path for a Hall element drive current which flows between the first electrode and the third electrode. The second line passes a center of the vertical Hall element, and a center point of a region which reaches the highest temperature in the circuit during an operation of the vertical Hall element lies on the second straight line.Type: ApplicationFiled: January 23, 2020Publication date: August 6, 2020Inventors: Takaaki HIOKA, Tomoki HIKICHI
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Publication number: 20200152861Abstract: A semiconductor devices has a vertical Hall element formed on a semiconductor substrate, the vertical Hall element including a semiconductor layer of a second conductivity type formed above the semiconductor substrate; an impurity diffusion layer of the second conductivity type formed in an upper portion of the semiconductor layer and having a concentration higher than that of the semiconductor layer; a plurality of electrodes formed on a surface of the impurity diffusion layer, arrayed in a straight line, and each formed from an impurity region of the second conductivity type; a plurality of electrode isolation diffusion layers of the first conductivity type each formed between two adjacent electrodes; and a buried layer formed between the semiconductor substrate and the semiconductor layer, and having a concentration higher than that of the semiconductor layer and lower than that of the impurity diffusion layer.Type: ApplicationFiled: October 25, 2019Publication date: May 14, 2020Inventor: Takaaki HIOKA
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Patent number: 10615333Abstract: The vertical Hall element includes: a semiconductor layer of a second conductivity type formed on a semiconductor substrate of a first conductivity type; a first electrode set formed in a surface of the semiconductor layer and including a first drive current supply electrode, a Hall voltage output electrode, and a second drive current supply electrode aligned along a straight line extending in a first direction in this order; and second to fifth electrode sets each having the same configuration as the configuration of the first electrode set and aligned with the first electrode set along a straight line extending in a second direction perpendicular to the first direction. The Hall voltage output electrode has a first depth, the first and second drive current supply electrodes have a second depth that is larger than the first depth.Type: GrantFiled: February 21, 2018Date of Patent: April 7, 2020Assignee: ABLIC INC.Inventor: Takaaki Hioka
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Publication number: 20200011942Abstract: A semiconductor device includes a semiconductor substrate 10 of a first conductivity type, a vertical Hall element 100 provided on the semiconductor substrate 10, and an excitation conductor 200 provided directly above the vertical Hall element 100 with an intermediation of an insulating film 30. The vertical Hall element 100 includes a semiconductor layer 101 of a second conductivity type provided on the semiconductor substrate 10, and a plurality of electrodes 111 through 115 each constituted from a high-concentration second conductivity type impurity region and provided on the surface of the semiconductor layer 101 along a straight line. A ratio WC/WH between a width WC of the excitation conductor 200 and a width WH of each of the plurality of electrodes 111 through 115 satisfies 0.3?WC/WH?1.0.Type: ApplicationFiled: June 18, 2019Publication date: January 9, 2020Inventors: Takaaki HIOKA, Hirotaka UEMURA
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Patent number: 10504957Abstract: A semiconductor device includes a semiconductor substrate having a plurality of Hall elements formed therein, and a magnetic body formed on the semiconductor substrate and having a magnetic flux converging function. The contour in a vertical cross section of the magnetic body on the semiconductor substrate has an outer circumferential portion. At least a part of the outer circumferential portion has a curve-shaped portion and a portion substantially parallel to the semiconductor substrate. A gap is formed between the semiconductor substrate and the portion of the magnetic body that is substantially parallel to the semiconductor substrate, and the gap lies above the entire top surfaces of the Hall elements. The magnetic body has at least a part of a structure made of non-magnetic substance embedded therein.Type: GrantFiled: March 13, 2017Date of Patent: December 10, 2019Assignee: ABLIC Inc.Inventors: Matsuo Kishi, Miei Takahama (nee Sato), Hiroshi Takahashi, Mika Ebihara, Takaaki Hioka
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Publication number: 20190355899Abstract: A Hall element includes a magnetic sensing portion formed of an impurity diffusion layer of a second conductivity type, and having four ends, and four electrodes provided at the respective four ends. The impurity diffusion layer forming the magnetic sensing portion has a first depth from a surface of the semiconductor substrate, has a first concentration gradient in which a concentration of impurities of the second conductivity type increases in a depth direction from the surface of the semiconductor substrate to a second depth which is shallower than the first depth, and has a second concentration gradient in which the concentration of the impurities of the second conductivity type decreases in the depth direction from the second depth to the first depth. The second depth is half the first depth or less, and the first concentration gradient is steeper than the second concentration gradient.Type: ApplicationFiled: May 15, 2019Publication date: November 21, 2019Inventor: Takaaki Hioka
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Publication number: 20190326507Abstract: A semiconductor device includes a first and a second vertical Hall elements formed parallel to each other. Each of the first and the second vertical Hall elements includes: a semiconductor layer on the semiconductor substrate; a Hall voltage output electrode and a first and a second drive current supply electrodes each formed of an impurity region, and sequentially arranged along a straight line on the semiconductor layer; and a first electrode isolation diffusion layer between the first drive current supply electrode and the Hall voltage output electrode, and a second electrode isolation diffusion layer between the Hall voltage output electrode and the second drive current supply electrode. The first and the second drive current supply electrodes each has the second depth deeper than the first depth of the Hall voltage output electrode and the depth of each of the electrode isolation diffusion layers.Type: ApplicationFiled: April 22, 2019Publication date: October 24, 2019Inventor: Takaaki HIOKA
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Patent number: 10429453Abstract: The magnetic sensor includes a semiconductor substrate having Hall elements on a front surface of the semiconductor substrate, an adhesive layer formed on a back surface of the semiconductor substrate, and a magnetic flux converging plate formed on the adhesive layer. The magnetic flux converging plate is formed on the back surface of the semiconductor substrate through formation of the magnetic flux converging plate by electroplating on a base conductive layer formed on a plating substrate prepared separately from the semiconductor substrate, application of an adhesive for forming the adhesive layer onto a surface of the magnetic flux converging plate so that the magnetic flux converging plate adheres to the back surface of the semiconductor substrate, and peeling off of the plating substrate afterward from the base conductive layer formed on the magnetic flux converging plate.Type: GrantFiled: March 14, 2017Date of Patent: October 1, 2019Assignee: ABLIC INC.Inventors: Takaaki Hioka, Mika Ebihara, Hiroshi Takahashi, Matsuo Kishi, Miei Takahama
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Publication number: 20190296227Abstract: The semiconductor device includes a vertical Hall element that is provided in a first region of a semiconductor substrate and has a plurality of first electrodes, and a resistive element that is provided in a second region different from the first region in the semiconductor substrate and has a plurality of second electrodes. The plurality of first electrodes and the plurality of second electrodes are connected so that resistances of current paths are substantially the same in any phase in which the vertical Hall element is driven using a spinning current method.Type: ApplicationFiled: March 25, 2019Publication date: September 26, 2019Applicant: ABLIC Inc.Inventors: Takaaki HIOKA, Tomoki HIKICHI
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Publication number: 20190285708Abstract: The semiconductor device includes a first vertical Hall element provided in a first region of a semiconductor substrate, and including a first plurality of electrodes arranged at predetermined intervals on a first straight line, a second vertical Hall element provided in a second region of the semiconductor substrate different from the first region, and including a second plurality of electrodes of the same number as that of the first plurality of electrodes, the second plurality of electrodes being arranged at the predetermined intervals on a second straight line parallel to the first straight line, a first drive power source configured to drive the first vertical Hall element, and a second drive power source configured to drive the second vertical Hall element and provided separately from the first drive power source.Type: ApplicationFiled: March 11, 2019Publication date: September 19, 2019Inventors: Takaaki Hioka, Tomoki Hikichi
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Patent number: 10290677Abstract: A semiconductor device includes a semiconductor substrate having a plurality of Hall elements formed therein, and a magnetic body formed on the semiconductor substrate and having a magnetic flux converging function. The contour in vertical cross-section of the magnetic body on the semiconductor substrate has an outer circumferential portion. At least a part of the outer circumferential portion has a portion having an approximate quadrant shape, and a portion contiguous to the approximate quadrant portion and substantially parallel to the semiconductor substrate.Type: GrantFiled: March 13, 2017Date of Patent: May 14, 2019Assignee: ABLIC Inc.Inventors: Matsuo Kishi, Miei Takahama (nee Sato), Hiroshi Takahashi, Mika Ebihara, Takaaki Hioka
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Patent number: 10263176Abstract: A vertical Hall element having an improved sensitivity and reduced offset voltage includes: a second conductivity type semiconductor layer formed on a semiconductor substrate and having an impurity concentration that is distributed uniformly; a second conductivity type impurity diffusion layer formed on the semiconductor layer and having a concentration higher than in the semiconductor layer; a plurality of electrodes formed in a straight line on a surface of the impurity diffusion layer, and each formed from a second conductivity type impurity region that is higher in concentration than the impurity diffusion layer; and a plurality of first conductivity type electrode isolation diffusion layers each formed between two electrodes out of the plurality of electrodes on the surface of the impurity diffusion layer, to isolate the plurality of electrodes from one another.Type: GrantFiled: November 9, 2017Date of Patent: April 16, 2019Assignee: ABLIC INC.Inventors: Takaaki Hioka, Mika Ebihara