Abstract: A photosensor including first and second conductive layers disposed on a main surface and a back surface of a substrate is provided. A conductive via layer is disposed between the conductive layers. A light emitting element and an integrated circuit (IC) including a light receiving element are mounted on the first conductive layer. The photosensor includes a translucent covering member that covers the light emitting element and the IC together with the first conductive layer. The covering member includes a groove between the light emitting element and the IC in a plan view. The first conductive layer includes a first mounting portion on which the light emitting element is mounted and a second mounting portion on which the IC is mounted. The light emitting device is electrically connected to the IC via the first mounting portion, the conductive via layer, the second conductive layer and the second mounting portion.

Abstract: An optical sensor includes a substrate including a substrate main surface intersecting a thickness-wise direction, a light emitting element disposed on the substrate main surface, a light receiving element disposed on the substrate main surface, a transparent first cover disposed on the substrate main surface to cover the light emitting element, and a transparent second cover disposed on the substrate main surface to cover the light receiving element. The first cover and the second cover are spaced apart by a gap.

Abstract: In each E-class inverter, an internal voltage detection circuit detects an internal voltage of a resonant type power supply circuit or a matching circuit and adjusts a phase of a driving signal of a MOSFET based on a detected voltage. It is thus possible to match a phase of a current voltage of a sine waveform of each inverter and combine power highly efficiently. Since power combining is performed highly efficiently without using a variable capacitor and variable inductor, it is possible to suppress upsizing of elements and achieve downsizing of a power amplifier circuit.

Abstract: In each E-class inverter, an internal voltage detection circuit detects an internal voltage of a resonant type power supply circuit or a matching circuit and adjusts a phase of a driving signal of a MOSFET based on a detected voltage. It is thus possible to match a phase of a current voltage of a sine waveform of each inverter and combine power highly efficiently. Since power combining is performed highly efficiently without using a variable capacitor and variable inductor, it is possible to suppress upsizing of elements and achieve downsizing of a power amplifier circuit.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor element, a plurality of terminals, and a sealing resin. The semiconductor element has a front surface and a back surface. The front surface and the back surface face in opposite directions to each other in a thickness direction of the semiconductor element. The plurality of terminals are disposed at a distance from the semiconductor element and are electrically connected to the front surface. The sealing resin has a first surface facing in a same direction as the direction in which the front surface faces. Each of the plurality of terminals has a main surface exposed from the first surface.

Abstract: A semiconductor device includes a Hall element, a sealing resin and at least one mount surface. The Hall element includes a functional surface and at least one electrode provided on the functional surface. The sealing resin includes a resin obverse surface and a resin reverse surface spaced apart from each other in a thickness direction, and covers at least a portion of the Hall element. The mount surface is electrically connected to the electrode of the Hall element and exposed from the resin reverse surface. The Hall element includes an exposed surface opposite to the functional surface. The exposed surface is flush with either one of the resin obverse surface and the resin reverse surface.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor element, a plurality of terminals, and a sealing resin. The semiconductor element has a front surface and a back surface. The front surface and the back surface face in opposite directions to each other in a thickness direction of the semiconductor element. The plurality of terminals are disposed at a distance from the semiconductor element and are electrically connected to the front surface. The sealing resin has a first surface facing in a same direction as the direction in which the front surface faces. Each of the plurality of terminals has a main surface exposed from the first surface.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor element, a plurality of terminals, and a sealing resin. The semiconductor element has a front surface and a back surface. The front surface and the back surface face in opposite directions to each other in a thickness direction of the semiconductor element. The plurality of terminals are disposed at a distance from the semiconductor element and are electrically connected to the front surface. The sealing resin has a first surface facing in a same direction as the direction in which the front surface faces. Each of the plurality of terminals has a main surface exposed from the first surface.

Abstract: A semiconductor device includes a Hall element, a sealing resin and at least one mount surface. The Hall element includes a functional surface and at least one electrode provided on the functional surface. The sealing resin includes a resin obverse surface and a resin reverse surface spaced apart from each other in a thickness direction, and covers at least a portion of the Hall element. The mount surface is electrically connected to the electrode of the Hall element and exposed from the resin reverse surface. The Hall element includes an exposed surface opposite to the functional surface. The exposed surface is flush with either one of the resin obverse surface and the resin reverse surface.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor element, a plurality of terminals, and a sealing resin. The semiconductor element has a front surface and a back surface. The front surface and the back surface face in opposite directions to each other in a thickness direction of the semiconductor element. The plurality of terminals are disposed at a distance from the semiconductor element and are electrically connected to the front surface. The sealing resin has a first surface facing in a same direction as the direction in which the front surface faces. Each of the plurality of terminals has a main surface exposed from the first surface.

Abstract: A series connection of a pair of dividing capacitors and a series connection of a PNP transistor and an NPN transistor are connected in parallel with a direct current voltage source, a primary winding of a saturable transformer is coupled between the junctions of the respective series connections, the saturable transformer comprising a pair of feedback windings coupled to the primary winding, the pair of feedback windings are connected between the base and emitter electrodes of the respective corresponding transistors through the respective base resistors, the emitter electrodes of the respective transistors being connected to the direct current voltage source sides, a series connection of two capacitors is connected between the junctions of the respective feedback windings and base resistors, and the junction of the two capacitors is connected to the junction of the series connection of the dividing capacitors.