Abstract: A stacked module includes stacked multiple boards having components mounted thereon, a connection component electrically connecting the stacked boards, and a feeding/cooling mechanism configured to feed the boards and to cool the components mounted on the boards. The feeding/cooling mechanism includes a cooling member that is inserted between the stacked, electrically connected boards and that is in contact with and cools the components mounted on the boards and a feeding member that is in contact with and feeds the boards.

Abstract: A stacked module includes stacked multiple boards having components mounted thereon, a connection component electrically connecting the stacked boards, and a feeding/cooling mechanism configured to feed the boards and to cool the components mounted on the boards. The feeding/cooling mechanism includes a cooling member that is inserted between the stacked, electrically connected boards and that is in contact with and cools the components mounted on the boards and a feeding member that is in contact with and feeds the boards.

Abstract: A polyphase clock generator for use in clock data recovery (CDR) includes a phase selector and a four-to-eight phase converter further including a plurality of delay paths, switches, and phase interpolators. The switches switch over the delay paths so as to select a group of delay paths suited to a clock frequency which is determined in advance. A plurality of reference clock signals with a predetermined phase difference (e.g. 90°) therebetween is selectively delayed while passing through the selected group of delay paths. The phase interpolators interpolate the delayed reference clock signals, passing through the selected group of delay paths, into the reference clock signals, thus generating a plurality of clock signals. The phase selector selectively combines the clock signals with a mixing ratio according to clock data recovery, thus generating a plurality of recovery clock signals with a precise phase difference (e.g.) 45°) therebetween.

Abstract: A polyphase clock generator for use in clock data recovery (CDR) includes a phase selector and a four-to-eight phase converter further including a plurality of delay paths, switches, and phase interpolators. The switches switch over the delay paths so as to select a group of delay paths suited to a clock frequency which is determined in advance. A plurality of reference clock signals with a predetermined phase difference (e.g. 90°) therebetween is selectively delayed while passing through the selected group of delay paths. The phase interpolators interpolate the delayed reference clock signals, passing through the selected group of delay paths, into the reference clock signals, thus generating a plurality of clock signals. The phase selector selectively combines the clock signals with a mixing ratio according to clock data recovery, thus generating a plurality of recovery clock signals with a precise phase difference (e.g.) 45°) therebetween.

Abstract: The multiphase clock generation circuit includes a variable slew rate circuit and a phase interpolation circuit. In the variable slew rate circuit, the slew rate varies according to a first control signal. Two reference clocks having a phase difference of 90° from each other are supplied to the phase interpolation circuit via the variable slew rate circuit. The phase interpolation circuit interpolates the two reference clocks having a phase difference of 90° from each other according to a second control signal to thereby generate an output clock having an intermediate phase.

Abstract: The multiphase clock generation circuit includes a variable slew rate circuit and a phase interpolation circuit. In the variable slew rate circuit, the slew rate varies according to a first control signal. Two reference clocks having a phase difference of 90° from each other are supplied to the phase interpolation circuit via the variable slew rate circuit. The phase interpolation circuit interpolates the two reference clocks having a phase difference of 90° from each other according to a second control signal to thereby generate an output clock having an intermediate phase.

Abstract: A delay means, in response to a delay control signal, performs delay control of the phase of a clock input signal, and outputs it. A selector means, during a speed test, selects a clock input signal from among a clock input signal from a delay unit, and the input signal from an external terminal. A conversion means samples the signal outputted from the selector means based on the sampling clock signal, converts a signal format and outputs it. A clock data recovery means generates a sampling clock signal having a phase depending on the signal inputted to the conversion means, and supplies it to the conversion means. By monitoring the control code for controlling the phase of the sampling clock, a correlation is obtained between a delay variation amount and a code variation amount, and a speed test is performed.

Abstract: Provided is a semiconductor integrated circuit which includes a logical operation circuit, a clock generator, a relay circuit, and a signal generating unit that are integrated. The clock generator generates multiphase clocks. The relay circuit distributes the generated multiphase clocks to the logical operation circuit. The signal generating unit detects phase states of the distributed multiphase clocks and, based on the detected phase states, generates an analog voltage signal having a voltage value indicative of a phase error in the multiphase clocks.

Abstract: Provided is a semiconductor integrated circuit which includes a logical, operation circuit, a clock generator, a relay circuit, and a signal generating unit that are integrated. The clock generator generates multiphase clocks. The relay circuit distributes the generated multiphase clocks to the logical operation circuit. The signal generating unit detects phase states of the distributed multiphase clocks and, based on the detected phase states, generates an analog voltage signal having a voltage value indicative of a phase error in the multiphase clocks.

Abstract: An output buffer with a pre-emphasis function to deliver a logic signal to a transmission line as a distributed constant circuit includes a first buffer to receive a first signal assigning a logical value to a logic signal to thereby drive the transmission line, a second buffer to receive a second signal having a predetermined logical relationship with the first signal to thereby drive the line in cooperation with the first buffer, and a unit to detect a change in the logical value of the logic signal. The second buffer is higher in output impedance than the first buffer on condition that attenuation of a signal through the line is reduced. If a de-emphasis state continues, a data generator creates a control signal such that the second buffer cooperates with the first buffer to drive the transmission line. The output buffer circuits therefore operate with low power consumption even if the de-emphasis state continues.

Abstract: A delay means, in response to a delay control signal, performs delay control of the phase of a clock input signal, and outputs it. A selector means, during a speed test, selects a clock input signal from among a clock input signal from a delay unit, and the input signal from an external terminal. A conversion means samples the signal outputted from the selector means based on the sampling clock signal, converts a signal format and outputs it. A clock data recovery means generates a sampling clock signal having a phase depending on the signal inputted to the conversion means, and supplies it to the conversion means. By monitoring the control code for controlling the phase of the sampling clock, a correlation is obtained between a delay variation amount and a code variation amount, and a speed test is performed.

Abstract: An output buffer circuit having a so-called pre-emphasis function of emphasizing a signal waveform in data transmission in an information processing device or the like according to an attenuation of a transmission line, includes a first buffer which receives input of an input signal which gives a logical value of a signal to drive the transmission line and a second buffer which drives the transmission line in cooperation with the first buffer, thereby cutting off, at the time of de-pre-emphasis when the pre-emphasis function is disabled, current flowing through the second buffer.

Abstract: An output buffer with a pre-emphasis function to deliver a logic signal to a transmission line as a distributed constant circuit includes a first buffer to receive a first signal assigning a logical value to a logic signal to thereby drive the transmission line, a second buffer to receive a second signal having a predetermined logical relationship with the first signal to thereby drive the line in cooperation with the first buffer, and a unit to detect a change in the logical value of the logic signal. The second buffer is higher in output impedance than the first buffer on condition that attenuation of a signal through the line is reduced. If a de-emphasis state continues, a data generator creates a control signal such that the second buffer cooperates with the first buffer to drive the transmission line. The output buffer circuits therefore operate with low power consumption even if the de-emphasis state continues.

Abstract: An output buffer circuit having a so-called pre-emphasis function of emphasizing a signal waveform in data transmission in an information processing device or the like according to an attenuation of a transmission line, including a first buffer which receives input of an input signal which gives a logical value of a signal to drive the transmission line and a second buffer which drives the transmission line in cooperation with the first buffer, thereby cutting off, at the time of de-pre-emphasis when the pre-emphasis function is disable, current flowing through the second buffer.

Abstract: An output buffer circuit having a function of accomplishing pre-emphasis, and transmitting a logic signal to a transmission line acting as a distributed parameter circuit, includes (a) a first buffer which receives a first logic signal defining a logical value of a logic signal to be transmitted to the transmission line, and drives the transmission line, and (b) a second buffer which receives a second logic signal having a predetermined logical relation with the first logic signal, and cooperates with the first buffer to drive the transmission line. The second buffer has an output impedance higher than an output impedance of the first buffer as long as attenuation in a signal in the transmission line is improved.

Abstract: A signal transmission system of the present invention has an output impedance Zs of a driving circuit, a characteristic impedance ZsO of the first transmission line, and a characteristic impedance ZO of a second transmission line are adjusted to satisfy a mathematical relation of: Zs<ZsO<ZO to provide a waveform of input of a receiving circuit with an overshoot characteristic. In the signal transmission system of the present invention, furthermore, ma time obtained by doubling a transmission time of the first transmission line with Ls in line length is shorter than a rise time Tr and a fall time Tf of the signal at an output end of the second transmission line.

Abstract: An output buffer circuit having a function of accomplishing preemphasis, and transmitting a logic signal to a transmission line acting as a distributed parameter circuit, includes (a) a first buffer which receives a first logic signal defining a logical value of a logic signal to be transmitted to the transmission line, and drives the transmission line, and (b) a second buffer which receives a second logic signal having a predetermined logical relation with the first logic signal, and cooperates with the first buffer to drive the transmission line. The second buffer has an output impedance higher than an output impedance of the first buffer as long as attenuation in a signal in the transmission line is improved.