Abstract: A correlation between noise injection time at which a power supply noise signal is applied to a clock path and a path delay of the clock path at the time of the power supply noise signal being applied is acquired. Furthermore, noise injection time width based on a clock signal inputted from a circuit arranged before the clock path to the clock path is set. The differences between path delays within the set noise injection time width are calculated by the use of the acquired correlation and the maximum value of the differences is estimated to be clock jitter of the clock path. The estimated clock jitter is smaller than the worst value and overestimation is prevented.

Abstract: A correlation between noise injection time at which a power supply noise signal is applied to a clock path and a path delay of the clock path at the time of the power supply noise signal being applied is acquired. Furthermore, noise injection time width based on a clock signal inputted from a circuit arranged before the clock path to the clock path is set. The differences between path delays within the set noise injection time width are calculated by the use of the acquired correlation and the maximum value of the differences is estimated to be clock jitter of the clock path. The estimated clock jitter is smaller than the worst value and overestimation is prevented.

Abstract: A design apparatus preferentially selects a low coefficient in a range in which design conditions are met from a group of coefficients (coefficient library) indicative of an increase in delay time at the time of voltage drop for combinations of one of a plurality of clock buffers which differ in parameter and one of a plurality of wiring loads, which differ in parameter, connected to the one of the plurality of clock buffers, selects from the plurality of clock buffers and the plurality of wiring loads a clock buffer and a wiring load each having a parameter associated with the selected coefficient, and designs a clock path.

Abstract: A semiconductor device includes an element coupled between a first power supply line and a second power supply line, and a capacitor coupled between the first power supply line and the second power supply line. A capacitance value of the capacitor is estimated based on a first value that depends on a period of a change in an input signal input to the element and a change in an output signal output from the element, and a second value that depends on a voltage between the first power supply line and the second power supply line.

Abstract: A method for laying out decoupling cells in a semiconductor integrated circuit including a plurality of paths. The method includes extracting from a timing analysis result a timing slack amount as a timing margin for power supply noise in one of the paths serving as a target path, converting the extracted timing margin to a noise tolerance amount, comparing the noise tolerance amount and a power supply noise amount of the target path, and determining whether or not a decoupling cell must be additionally laid out in the target path based on the comparison result.

Abstract: A semiconductor device includes an element coupled between a first power supply line and a second power supply line, and a capacitor coupled between the first power supply line and the second power supply line. A capacitance value of the capacitor is estimated based on a first value that depends on a period of a change in an input signal input to the element and a change in an output signal output from the element, and a second value that depends on a voltage between the first power supply line and the second power supply line.

Abstract: A method for laying out decoupling cells in a semiconductor integrated circuit including a plurality of paths. The method includes extracting from a timing analysis result a timing slack amount as a timing margin for power supply noise in one of the paths serving as a target path, converting the extracted timing margin to a noise tolerance amount, comparing the noise tolerance amount and a power supply noise amount of the target path, and determining whether or not a decoupling cell must be additionally laid out in the target path based on the comparison result.

Abstract: An event driven system for testing logical operations of logic elements of an integrated circuit including an oscillation element. The system uses in/out data of the logic elements and net-list data of the logic circuit. An incoming event of the oscillator element has a signal incoming time and a signal incoming place, indicating a change in a signal by oscillation of the oscillation element. An incoming process of the incoming event includes generating a normal event having the same incoming time and the same incoming place as the incoming event, and generating a new incoming event having the same incoming time as the incoming event, but a different incoming time. The different incoming time is a changing time of a signal caused by oscillation of the oscillator element. The changing time is later than the incoming time of the incoming event.

Abstract: A method is disclosed to execute an event driven logic simulation to check the function of a logic circuit, by using a logic simulator. The logic simulator includes at least one data base and a processing unit having a dummy element synthesizer. The dummy element is a tool for detecting changes in signals at a target cell or a target terminal. At the time that the logic simulation starts, the dummy element synthesizer produces the dummy element defining data, referring to or based on information stored in the data base, and combines the dummy element defining data and the logic circuit design data. Thus, for example, timing simulation at a target cell in the logic circuit or the check of the number of times of changes in signals at a target output terminal of the logic circuit, is executed during the event driven logic simulation.

Abstract: A three dimensional object under test is measured to obtain shape data representing a shape of the three dimensional object. The object under test is measured using, for example, an ultrasonic probe LED to obtain defect test data. A processing mechanism forms a three-dimensional graphic image of a defect zone from the defect test data and a three-dimensional graphic image of the object under test from the shape data. A display mechanism is provided for displaying the three-dimensional graphic image of the defect zone superimposed over the three-dimensional graphic image of the object under test.

Abstract: A radiographic test is conducted on a welded portion of a pipe or the like to form a radiographic image, which is introduced into a computer. Volumetric defects and planar defects in the radiographic image are emphasized and extracted by separate methods to obtain a volumetric candidate defect image and a planar candidate defect image. The candidate defect images are then combined to form a single image in which defects can be easily identified. Features of defects in the images are measured, and a set of interference rules is applied to the measured features. Each inference rule gives a degree of certainty that a defect is of a certain type. The degrees of certainty determined by a plurality of the rules are collated to obtain a total degree of certainty, and the type of a defect is inferred from the total degree of certainty.