Abstract: In a silicon wafer having an oxygen precipitate layer, a depth of DZ layer ranging from a wafer surface to an oxygen precipitate layer is 2 to 10 ?m and an oxygen precipitate concentration of the oxygen precipitate layer is not less than 5×107 precipitates/cm3.

Abstract: There is provided a production method in which the beveling step conducted for preventing the cracking or chipping in a raw wafer during the grinding can be omitted when the raw wafer cut out from a crystalline ingot is processed into a double-side mirror-finished semiconductor wafer and a semiconductor wafer can be obtained cheaply by shortening the whole of the production steps for the semiconductor wafer and decreasing the machining allowance of silicon material in the semiconductor wafer to reduce the kerf loss of the semiconductor material as compared with the conventional method.

Abstract: There is provided a silicon wafer surface defect evaluation method capable of readily detecting a region where small crystal defects exist, the evaluation method comprising: a rapid heat treatment step of a silicon wafer from a silicon single-crystal ingot in an atmosphere which can nitride silicon at a temperature elevating speed of 10 to 150° C./second from a room temperature to temperatures between not lower than 1170° C. and less than a silicon melting point, holding the silicon wafer at the processing temperature for 1 to 120 seconds and then cooling the silicon wafer to the room temperature at a temperature lowering speed of 10 to 100° C./second; and a step of using a surface photo voltage method to calculate a minority carrier diffusion length on the wafer surface, thereby detecting a region on the wafer surface in which small COP's which cannot be detected at least by a particle counter exist.

Abstract: In a silicon wafer having an oxygen precipitate layer, a depth of DZ layer ranging from a wafer surface to an oxygen precipitate layer is 2 to 10 ?m and an oxygen precipitate concentration of the oxygen precipitate layer is not less than 5×107 precipitates/cm3.

Abstract: This method for manufacturing an SOI wafer includes: a step of subjecting a mirror-polished active layer wafer to a rapid thermal annealing treatment; a step of forming insulating films in a front surface and a rear surface of the active layer wafer; a step of bonding the active layer wafer and a support wafer with the insulating film therebetween so as to form a bonded wafer; a step of loading the bonded wafer on a wafer boat in a state such that a portion of the active layer wafer is in contact with the wafer boat, and then subjecting the bonded wafer to a heat treatment for bonding enhancement which enhances a bonding strength between the active layer wafer and the support wafer in the bonded wafer; and a step of thinning a portion of the active layer wafer.

Abstract: This method for manufacturing an SOI wafer includes: a step of forming insulating films in a front surface and a mirror-polished rear surface of an active layer wafer; a step of removing the insulating film in the front surface of the active layer wafer; a step of subjecting the active layer wafer to a rapid thermal annealing process; a step of bonding the active layer wafer and a support wafer with the insulating film formed in the rear surface therebetween so as to form a bonded wafer; a step of subjecting the bonded wafer to a heat treatment for bonding enhancement which enhances a bonding strength between the active layer wafer and the support wafer; and a step of thinning the active layer wafer in the bonded wafer so as to form an SOI layer.

Abstract: There is provided a silicon wafer surface defect evaluation method capable of readily detecting a region where small crystal defects exist. A silicon wafer surface defect evaluation method according to the present invention is characterized by comprising: a rapid heat treatment step of applying a heat treatment to a silicon wafer cut out from a silicon single-crystal ingot in an atmosphere which can nitride silicon at a temperature elevating speed of 10 to 150° C./second from a room temperature to temperatures between not lower than 1170° C. and less than a silicon melting point, holding the silicon wafer at the processing temperature for 1 to 120 seconds and then cooling the silicon wafer to the room temperature at a temperature lowering speed of 10 to 100° C.

Abstract: A silicon wafer wherein stacking fault (SF) nuclei are distributed throughout the entire in-plane direction, and the density of the stacking fault nuclei is set to a range of between 0.5×108 cm?3 and 1×1011 cm?3.

Abstract: This method for manufacturing an SOI wafer includes: a step of forming insulating films in a front surface and a mirror-polished rear surface of an active layer wafer; a step of removing the insulating film in the front surface of the active layer wafer; a step of subjecting the active layer wafer to a rapid thermal annealing process; a step of bonding the active layer wafer and a support wafer with the insulating film formed in the rear surface therebetween so as to form a bonded wafer; a step of subjecting the bonded wafer to a heat treatment for bonding enhancement which enhances a bonding strength between the active layer wafer and the support wafer; and a step of thinning the active layer wafer in the bonded wafer so as to form an SOI layer.

Abstract: This method for manufacturing an SOI wafer includes: a step of subjecting a mirror-polished active layer wafer to a rapid thermal annealing treatment; a step of forming insulating films in a front surface and a rear surface of the active layer wafer; a step of bonding the active layer wafer and a support wafer with the insulating film therebetween so as to form a bonded wafer; a step of loading the bonded wafer on a wafer boat in a state such that a portion of the active layer wafer is in contact with the wafer boat, and then subjecting the bonded wafer to a heat treatment for bonding enhancement which enhances a bonding strength between the active layer wafer and the support wafer in the bonded wafer; and a step of thinning a portion of the active layer wafer.

Abstract: A silicon wafer wherein stacking fault (SF) nuclei are distributed throughout the entire in-plane direction, and the density of the stacking fault nuclei is set to a range of between 0.5×108 cm−3 and 1×1011 cm−3.

Abstract: An ingot is manufactured by pulling it up such that V/Ga and V/Gb become 0.23 to 0.50 mm2/minute. ° C., respectively, where V (mm/minute) is a pulling-up speed, and Ga (° C./mm) is an axial temperature gradient at the center of the ingot and Gb (° C./mm) is an axial temperature gradient at the edge of the ingot at temperatures in a range of 1,300° C. to a melting point of silicon. A wafer obtained by slicing the ingot is heat treated in a reductive atmosphere at temperatures in a range of 1,050° C. to 1,220° C. for 30 to 150 minutes. A silicon wafer free of OSF's, tree of COP's, and substantially free of contamination such as Fe and of occurrence of slip, is obtained.

Abstract: A method of heat-treating a silicon wafer has the steps of: preparing a silicon wafer having an oxygen concentration of 1.2×1018 atoms/cm3 or less (old ASTM) without generating crystal originated particles(COP'S) and interstitial-type large dislocation(L/D); forming a polysilicon layer of 0.1 &mgr;m to 1.6 &mgr;m in thickness on a back of the silicon wafer by a chemical-vapor deposition at a temperature of 670° C.±30° C.; and heat-treating the silicon wafer having the polysilicon layer in an oxygen atmosphere at 1000° C.±30° C. for 2 to 5 hours and subsequently at 1130° C.±30° C. for 1 to 16 hours. In this method, the silicon wafer before the formation of the polysilicon layer thereon is the type of a wafer in which oxidation induced stacking faults(OSF's) manifest itself at a center of the wafer when the wafer is subjected to the heat-treatment.

Abstract: An ingot is manufactured by pulling it up such that V/Ga and V/Gb become 0.23 to 0.50 mm2/minute ° C., respectively, where V (mm/minute) is a pulling-up speed, and Ga (° C./mm) is and axial temperature gradient at the center of the ingot and Gb (° C./mm) is an axial temperature gradient at the edge of the ingot at temperatures in a range of 1,300° C. to a melting pointy of silicon. A wafer obtained by slicing the ingot is heat treated in a reductive atmosphere at temperature in a renge of 1,050° C. to 1,220° C. for 30 to 150 minutes. A silicon wafer free of OSF's, free of COP's, and substantially free of contamination such as Fe and of occurence of slip, is obtained.

Abstract: A method of heat-treating a silicon wafer has the steps of: preparing a silicon wafer having an oxygen concentration of 1.2×1018 atoms/cm3 or less (old ASTM) without generating crystal originated particles(COP'S) and interstitial-type large dislocation(L/D); forming a polysilicon layer of 0.1 &mgr;m to 1.6 &mgr;m in thickness on a back of the silicon wafer by a chemical-vapor deposition at a temperature of 670° C.±30° C.; and heat-treating the silicon wafer having the polysilicon layer in an oxygen atmosphere at 1000° C.±30° C. for 2 to 5 hours and subsequently at 1130° C.±30° C. for 1 to 16 hours. In this method, the silicon wafer before the formation of the polysilicon layer thereon is the type of a wafer in which oxidation induced stacking faults(OSF's) manifest itself at a center of the wafer when the wafer is subjected to the heat-treatment.

Abstract: A method of heat-treating a silicon wafer has the steps of: preparing a silicon wafer having an oxygen concentration of 1.2×1018 atoms/cm3 or less (old ASTM) without generating crystal originated particles(COP'S) and interstitial-type large dislocation(L/D); forming a polysilicon layer of 0.1 &mgr;m to 1.6 &mgr;m in thickness on a back of the silicon wafer by a chemical-vapor deposition at a temperature of 670° C.±30° C.; and heat-treating the silicon wafer having the polysilicon layer in an oxygen atmosphere at 1000° C.±30° C. for 2 to 5 hours and subsequently at 1130° C.±30° C. for 1 to 16 hours. In this method, the silicon wafer before the formation of the polysilicon layer thereon is the type of a wafer in which oxidation induced stacking faults(OSF's) manifest itself at a center of the wafer when the wafer is subjected to the heat-treatment.