Patents by Inventor Takaaki SUZAWA
Takaaki SUZAWA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11574840Abstract: In a contact hole of an interlayer insulating film, a tungsten film forming a contact plug is embedded via a barrier metal. The interlayer insulating film is formed by sequentially stacked HTO and BPSG films. The BPSG film has an etching rate faster than that of the HTO film with respect to a hydrofluoric acid solution used in wet etching of preprocessing before formation of the barrier metal. After the contact hole is formed in the interlayer insulating film, a width of an upper portion of the contact hole at the BPSG film is increased in a step-like shape, to be wider than a width of a lower portion at the HTO film by the wet etching before the formation of the barrier metal, whereby an aspect ratio of the contact hole is reduced. Thus, size reductions and enhancement of the reliability may be realized.Type: GrantFiled: October 7, 2021Date of Patent: February 7, 2023Assignee: FUJI ELECTRIC CO., LTD.Inventor: Takaaki Suzawa
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Publication number: 20220028735Abstract: In a contact hole of an interlayer insulating film, a tungsten film forming a contact plug is embedded via a barrier metal. The interlayer insulating film is formed by sequentially stacked HTO and BPSG films. The BPSG film has an etching rate faster than that of the HTO film with respect to a hydrofluoric acid solution used in wet etching of preprocessing before formation of the barrier metal. After the contact hole is formed in the interlayer insulating film, a width of an upper portion of the contact hole at the BPSG film is increased in a step-like shape, to be wider than a width of a lower portion at the HTO film by the wet etching before the formation of the barrier metal, whereby an aspect ratio of the contact hole is reduced. Thus, size reductions and enhancement of the reliability may be realized.Type: ApplicationFiled: October 7, 2021Publication date: January 27, 2022Applicant: FUJI ELECTRIC CO., LTD.Inventor: Takaaki SUZAWA
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Patent number: 11171042Abstract: In a contact hole of an interlayer insulating film, a tungsten film forming a contact plug is embedded via a barrier metal. The interlayer insulating film is formed by sequentially stacked HTO and BPSG films. The BPSG film has an etching rate faster than that of the HTO film with respect to a hydrofluoric acid solution used in wet etching of preprocessing before formation of the barrier metal. After the contact hole is formed in the interlayer insulating film, a width of an upper portion of the contact hole at the BPSG film is increased in a step-like shape, to be wider than a width of a lower portion at the HTO film by the wet etching before the formation of the barrier metal, whereby an aspect ratio of the contact hole is reduced. Thus, size reductions and enhancement of the reliability may be realized.Type: GrantFiled: October 22, 2019Date of Patent: November 9, 2021Assignee: FUJI ELECTRIC CO., LTD.Inventor: Takaaki Suzawa
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Publication number: 20200051852Abstract: In a contact hole of an interlayer insulating film, a tungsten film forming a contact plug is embedded via a barrier metal. The interlayer insulating film is formed by sequentially stacked HTO and BPSG films. The BPSG film has an etching rate faster than that of the HTO film with respect to a hydrofluoric acid solution used in wet etching of preprocessing before formation of the barrier metal. After the contact hole is formed in the interlayer insulating film, a width of an upper portion of the contact hole at the BPSG film is increased in a step-like shape, to be wider than a width of a lower portion at the HTO film by the wet etching before the formation of the barrier metal, whereby an aspect ratio of the contact hole is reduced. Thus, size reductions and enhancement of the reliability may be realized.Type: ApplicationFiled: October 22, 2019Publication date: February 13, 2020Applicant: FUJI ELECTRIC CO., LTD.Inventor: Takaaki SUZAWA
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Patent number: 8748225Abstract: A semiconductor device and manufacturing method are disclosed which prevent breakage and chipping of a semiconductor chip and improve device characteristics. A separation layer is in a side surface of an element end portion of the chip. An eave portion is formed by a depressed portion in the element end portion. A collector layer on the rear surface of the chip extends to a side wall and bottom surface of the depressed portion, and is connected to the separation layer. A collector electrode is over the whole surface of the collector layer, and is on the side wall of the depressed portion. The thickness of an outermost electrode film is 0.05 ?m or less. The collector electrode on the rear surface of the chip is joined onto an insulating substrate via a solder layer, which covers the collector electrode on a flat portion of the rear surface of the semiconductor chip.Type: GrantFiled: April 10, 2013Date of Patent: June 10, 2014Assignee: Fuji Electric Co., Ltd.Inventors: Kyohei Fukuda, Eiji Mochizuki, Mitsutoshi Sawano, Takaaki Suzawa
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Patent number: 8598688Abstract: A semiconductor device and manufacturing method are disclosed which prevent breakage and chipping of a semiconductor chip and improve device characteristics. A separation layer is in a side surface of an element end portion of the chip. An eave portion is formed by a depressed portion in the element end portion. A collector layer on the rear surface of the chip extends to a side wall and bottom surface of the depressed portion, and is connected to the separation layer. A collector electrode is over the whole surface of the collector layer, and is on the side wall of the depressed portion. The thickness of an outermost electrode film is 0.05 ?m or less. The collector electrode on the rear surface of the chip is joined onto an insulating substrate via a solder layer, which covers the collector electrode on a flat portion of the rear surface of the semiconductor chip.Type: GrantFiled: June 10, 2011Date of Patent: December 3, 2013Assignee: Fuji Electric Co., Ltd.Inventors: Kyohei Fukuda, Eiji Mochizuki, Mitsutoshi Sawano, Takaaki Suzawa
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Publication number: 20130237016Abstract: A semiconductor device and manufacturing method are disclosed which prevent breakage and chipping of a semiconductor chip and improve device characteristics. A separation layer is in a side surface of an element end portion of the chip. An eave portion is formed by a depressed portion in the element end portion. A collector layer on the rear surface of the chip extends to a side wall and bottom surface of the depressed portion, and is connected to the separation layer. A collector electrode is over the whole surface of the collector layer, and is on the side wall of the depressed portion. The thickness of an outermost electrode film is 0.05 ?m or less. The collector electrode on the rear surface of the chip is joined onto an insulating substrate via a solder layer, which covers the collector electrode on a flat portion of the rear surface of the semiconductor chip.Type: ApplicationFiled: April 10, 2013Publication date: September 12, 2013Applicant: FUJI ELECTRIC CO., LTD.Inventors: Kyohei FUKUDA, Eiji MOCHIZUKI, Mitsutoshi SAWANO, Takaaki SUZAWA
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Publication number: 20120313224Abstract: A semiconductor device and manufacturing method are disclosed which prevent breakage and chipping of a semiconductor chip and improve device characteristics. A separation layer is in a side surface of an element end portion of the chip. An eave portion is formed by a depressed portion in the element end portion. A collector layer on the rear surface of the chip extends to a side wall and bottom surface of the depressed portion, and is connected to the separation layer. A collector electrode is over the whole surface of the collector layer, and is on the side wall of the depressed portion. The thickness of an outermost electrode film is 0.05 ?m or less. The collector electrode on the rear surface of the chip is joined onto an insulating substrate via a solder layer, which covers the collector electrode on a flat portion of the rear surface of the semiconductor chip.Type: ApplicationFiled: June 10, 2011Publication date: December 13, 2012Applicant: FUJI ELECTRIC CO., LTD.Inventors: Kyohei FUKUDA, Eiji MOCHIZUKI, Mitsutoshi SAWANO, Takaaki SUZAWA