Abstract: The present technique relates to an electrostatic protective element that enables protective performance with respect to static electricity to be improved and to an electronic device.

Abstract: A liquid crystal display element includes a front panel, a back panel disposed facing the front panel, a liquid crystal material layer held between the front panel and the back panel, and a sealing part that is provided at a position surrounding a periphery of the liquid crystal material layer and establishes electric connection between the front panel and the back panel.

Abstract: The present technique relates to an electrostatic protective element that enables protective performance with respect to static electricity to be improved and to an electronic device.

Abstract: The present disclosure relates to a semiconductor device and an electronic apparatus that make it possible to provide a higher voltage resistance. An outer-peripheral structure region is provided in an n-type well on a surface of a semiconductor substrate, the outer-peripheral structure region being arranged to surround an outer periphery of a region in which a plurality of semiconductor elements is formed. Further, an anode is arranged in an innermost in the outer-peripheral structure region, and a plurality of guard rings is multiply arranged on an outside of the anode. Furthermore, a field plate covering the anode and a field plate covering a guard ring adjacent to the anode are formed to be electrically connected to each other so as to be combined. The present technology is applicable to, for example, various semiconductor devices.

Abstract: A semiconductor integrated circuit of the present disclosure includes: first power and second power supply lines that are coupled to a protected circuit; a third power supply line that is supplied with a voltage different from voltages supplied to the first and second power supply lines; a detection circuit that is coupled between the first and second power supply lines and detects a surge occurring in the first power supply line; an inverter circuit that includes one or more inverters coupled in series, and is coupled between the first and second power supply lines; a protection transistor that is coupled between the first and second power supply lines, and is controlled by an output of the detection circuit to cause the surge to flow through the second power supply line; and a time constant circuit that is coupled to at least the third power supply line and the protection transistor.

Abstract: Both an improvement of on-current and suppression of leakage current of a transistor are achieved. A transistor includes a drain, a source, a gate, and a gate insulating film. In the transistor, the gate insulating film is disposed between the source and the drain. In addition, in the transistor, the gate has a plurality of regions provided on a surface of the gate insulating film. In addition, in the gate, the plurality of regions provided on the gate insulating film have different work functions.

Abstract: The present disclosure relates to a semiconductor device and an electronic apparatus that make it possible to provide a higher voltage resistance. An outer-peripheral structure region is provided in an n-type well on a surface of a semiconductor substrate, the outer-peripheral structure region being arranged to surround an outer periphery of a region in which a plurality of semiconductor elements is formed. Further, an anode is arranged in an innermost in the outer-peripheral structure region, and a plurality of guard rings is multiply arranged on an outside of the anode. Furthermore, a field plate covering the anode and a field plate covering a guard ring adjacent to the anode are formed to be electrically connected to each other so as to be combined. The present technology is applicable to, for example, various semiconductor devices.

Abstract: A field-effect transistor including a gate electrode provided on a first-conductivity-type region of a semiconductor substrate with an insulating film provided between the gate electrode and the first-conductivity-type region, a source region of a second conductivity type provided in the semiconductor substrate on one of sides across the gate electrode, a drain region of the second conductivity type provided in the semiconductor substrate on the other of the sides, the other side facing the one side across the gate electrode, a first region of the first conductivity type provided below the drain region and having a higher concentration than the first-conductivity-type region, a second region of the first conductivity type provided to reach a surface in the semiconductor substrate on the other side and having a higher concentration than the first-conductivity-type region, and an extraction electrode connected to the second region.

Abstract: To provide a field-effect transistor and a semiconductor device with improved ESD resistance.

Abstract: Both an improvement of on-current and suppression of leakage current of a transistor are achieved. A transistor includes a drain, a source, a gate, and a gate insulating film. In the transistor, the gate insulating film is disposed between the source and the drain. In addition, in the transistor, the gate has a plurality of regions provided on a surface of the gate insulating film. In addition, in the gate, the plurality of regions provided on the gate insulating film have different work functions.

Abstract: A semiconductor integrated circuit of the present disclosure includes: first power and second power supply lines that are coupled to a protected circuit; a third power supply line that is supplied with a voltage different from voltages supplied to the first and second power supply lines; a detection circuit that is coupled between the first and second power supply lines and detects a surge occurring in the first power supply line; an inverter circuit that includes one or more inverters coupled in series, and is coupled between the first and second power supply lines; a protection transistor that is coupled between the first and second power supply lines, and is controlled by an output of the detection circuit to cause the surge to flow through the second power supply line; and a time constant circuit that is coupled to at least the third power supply line and the protection transistor.

Abstract: Provided is a method of driving a protective circuit, the protective circuit including a first clamp section and a second clamp section, the first clamp section including a first device, the first clamp section being configured to protect an entire protected circuit of a predetermined area when the first device is driven, the second clamp section including a second device, the second clamp section being configured to protect a predetermined device of the protected circuit when the second device is driven, the method comprising: connecting a predetermined spot of the first clamp section and the gate of the second device of the second clamp section; and causing the gate voltage of the second device to be the potential of the predetermined spot.

Abstract: A protection element includes a first wiring line configured to be supplied with a signal voltage when electric current is on; a second wiring line configured to be supplied with a criterion voltage; a detection circuit connected between the first wiring line and the second wiring line, and configured to detect the signal voltage inputted onto the first wiring line; an inverter circuit including a plurality of inverters connected between the first wiring line and the second wiring line, and configured to be supplied with a reference voltage having a same level as that of the signal voltage between an odd-numbered inverter and an even-numbered inverter when electric current is on; and a protection transistor connected between the first wiring line and the second wiring line, and having a gate configured to receive output of the inverter circuit.

Abstract: Provided is a method of driving a protective circuit, the protective circuit including a first clamp section and a second clamp section, the first clamp section including a first device, the first clamp section being configured to protect an entire protected circuit of a predetermined area when the first device is driven, the second clamp section including a second device, the second clamp section being configured to protect a predetermined device of the protected circuit when the second device is driven, the method comprising: connecting a predetermined spot of the first clamp section and the gate of the second device of the second clamp section; and causing the gate voltage of the second device to be the potential of the predetermined spot.

Abstract: Disclosed herein is a semiconductor integrated circuit including in a same semiconductor substrate: first and second power supply lines; a protected circuit being connected between the first and second power supply lines and provided with a supply voltage; a detecting circuit detecting a surge generated in the first power supply line; an inverter circuit having one or more inverters connected in series to each other; and a protection transistor being connected between the first and second power supply lines and controlled by output of the detecting circuit to discharge the surge to the second power supply line. In the inverter circuit, an inverter whose output is connected to a control node of the protection transistor is connected between the first power supply line and a third power supply line that is different from the first and second power supply lines.

Abstract: A protection element includes a first wiring line configured to be supplied with a signal voltage when electric current is on; a second wiring line configured to be supplied with a criterion voltage; a detection circuit connected between the first wiring line and the second wiring line, and configured to detect the signal voltage inputted onto the first wiring line; an inverter circuit including a plurality of inverters connected between the first wiring line and the second wiring line, and configured to be supplied with a reference voltage having a same level as that of the signal voltage between an odd-numbered inverter and an even-numbered inverter when electric current is on; and a protection transistor connected between the first wiring line and the second wiring line, and having a gate configured to receive output of the inverter circuit.

Abstract: Disclosed herein is a protection element for protecting a circuit element. The protection element includes source and drain areas created in a semiconductor layer, a gate created on the semiconductor layer, sandwiching a gate insulation film between the gate and the semiconductor layer, a source electrode connected to the surface of the source area and electrically connected to the ground, a drain electrode connected to the surface of the drain area and used for receiving a surge input, and a diode connected between the source electrode and the gate.

Abstract: Disclosed herein is a semiconductor integrated circuit including in a same semiconductor substrate: first and second power supply lines; a protected circuit being connected between the first and second power supply lines and provided with a supply voltage; a detecting circuit detecting a surge generated in the first power supply line; an inverter circuit having one or more inverters connected in series to each other; and a protection transistor being connected between the first and second power supply lines and controlled by output of the detecting circuit to discharge the surge to the second power supply line. In the inverter circuit, an inverter whose output is connected to a control node of the protection transistor is connected between the first power supply line and a third power supply line that is different from the first and second power supply lines.

Abstract: Disclosed herein is a protection element for protecting a circuit element. The protection element includes source and drain areas created in a semiconductor layer, a gate created on the semiconductor layer, sandwiching a gate insulation film between the gate and the semiconductor layer, a source electrode connected to the surface of the source area and electrically connected to the ground, a drain electrode connected to the surface of the drain area and used for receiving a surge input, and a diode connected between the source electrode and the gate.

Abstract: There is provided a method for simulating the electrical characteristics of an electronic device including a step of specifying the material, electrical characteristics, and shape of a part of interest of the electronic device, the specification of the shape being performed by selecting it from among several preselected simplified shape models to obtain required data easily. Further, it is possible to reuse such data as input data for various simulators. The data can be accurately created in a shorter period of time.