Abstract: An SBD includes: a terminal well region formed to surround an active region; a field insulating film formed to cover part of the terminal well region; a surface electrode formed on a drift layer on an inner side in relation to the field insulating film and electrically connected to the terminal well region; a surface protection film covering an end portion on an outer side of the surface electrode; and a back surface electrode formed on a back surface of a single crystal substrate. An end portion of an outer side of the surface electrode in the corner portion of the terminal region is located on an inner side in relation to the end portion of the outer side of the surface electrode in a straight portion of a terminal region based on a position of an end portion of an outer side of the terminal well region.

Abstract: The present disclosure relates to a silicon carbide semiconductor device, and includes a p-type second well region provided as an upper layer portion of a semiconductor layer; an n-type second impurity region provided as an upper layer portion of the second well region; a p-type second well contact region provided as an upper layer portion of the second well region; a field insulating film provided on the second well region; a second contact passed through the field insulating film electrically connected to a first main electrode; a boundary gate insulating film provided on a boundary between the element region and the non-element region; a boundary gate electrode provided on the boundary gate insulating film; and a second main electrode. The second well contact region extends from below the second contact toward the element region, and the second impurity region extends from below the second contact toward the non-element region.

Abstract: A drift layer and a source region have a first conductivity type. A base region has a second conductivity type. A first trench penetrates the source region and the base region. A gate electrode is provided in the first trench through a gate insulation film. A first relaxation region is disposed below the first trench, and has the second conductivity type. A source pad electrode is electrically connected to the first relaxation region. A gate pad electrode is disposed in a non-element region. An impurity region is disposed in the non-element region, is provided on the drift layer, and has the first conductivity type. A second trench penetrates the impurity region. A second relaxation region is disposed below the second trench, and has the second conductivity type.

Abstract: An SBD includes: a terminal well region formed to surround an active region; a field insulating film formed to cover part of the terminal well region; a surface electrode formed on a drift layer on an inner side in relation to the field insulating film and electrically connected to the terminal well region; a surface protection film covering an end portion on an outer side of the surface electrode; and a back surface electrode formed on a back surface of a single crystal substrate. An end portion of an outer side of the surface electrode in the corner portion of the terminal region is located on an inner side in relation to the end portion of the outer side of the surface electrode in a straight portion of a terminal region based on a position of an end portion of an outer side of the terminal well region.

Abstract: To provide a technique of reducing gate oscillation while suppressing reduction in switching speed. A semiconductor device according to the technique disclosed in the present description includes: a first gate electrode in an active region; a gate pad in a first region different from the active region in a plan view; and a first gate line electrically connecting the first gate electrode and the gate pad to each other. The first gate line is formed into a spiral shape. The first gate line is made of a different type of material from the first gate electrode.

Abstract: In an element region and a non-element region, a silicon carbide semiconductor device includes a drift layer having a first conductivity type provided on a silicon carbide semiconductor substrate. In the element region, the silicon carbide semiconductor device includes a first trench that reaches the drift layer, and a gate electrode provided in the first trench through a gate insulation film and electrically connected to a gate pad electrode. In the non-element region, the silicon carbide semiconductor device includes a second trench whose bottom surface reaches the drift layer, a second relaxation region having a second conductivity type disposed below the second trench, an inner-surface insulation film provided on a side surface and on the bottom surface of the second trench, and a low-resistance region provided in the second trench through the inner-surface insulation film and electrically insulated from the gate pad electrode.

Abstract: A drift layer and a source region have a first conductivity type. A base region has a second conductivity type. A first trench penetrates the source region and the base region. A gate electrode is provided in the first trench through a gate insulation film. A first relaxation region is disposed below the first trench, and has the second conductivity type. A source pad electrode is electrically connected to the first relaxation region. A gate pad electrode is disposed in a non-element region. An impurity region is disposed in the non-element region, is provided on the drift layer, and has the first conductivity type. A second trench penetrates the impurity region. A second relaxation region is disposed below the second trench, and has the second conductivity type.

Abstract: In an element region and a non-element region, a silicon carbide semiconductor device includes a drift layer having a first conductivity type provided on a silicon carbide semiconductor substrate. In the element region, the silicon carbide semiconductor device includes a first trench that reaches the drift layer, and a gate electrode provided in the first trench through a gate insulation film and electrically connected to a gate pad electrode. In the non-element region, the silicon carbide semiconductor device includes a second trench whose bottom surface reaches the drift layer, a second relaxation region having a second conductivity type disposed below the second trench, an inner-surface insulation film provided on a side surface and on the bottom surface of the second trench, and a low-resistance region provided in the second trench through the inner-surface insulation film and electrically insulated from the gate pad electrode.

Abstract: A silicon carbide semiconductor device includes a silicon carbide semiconductor substrate having an n-type drift layer, and a p-type well region formed in a surface portion of a part of the drift layer, an insulating film provided on the well region, a gate built-in resistor formed of polysilicon in contact with a surface of the insulating film, an interlayer insulating film formed on the gate built-in resistor, a gate contact wire that is connected to a gate pad and formed on the interlayer insulating film, a gate wire provided on the interlayer insulating layer so as to be apart from the gate contact wire, a first gate contact for electrically connecting the gate contact wire and the gate built-in resistor, and a second gate contact for electrically connecting the gate wire and the gate built-in resistor.

Abstract: A silicon carbide semiconductor device includes: a pair of first well regions separated by distance W1 in surface layer portions of a silicon carbide drift layer and having p-type impurity concentration higher than n-type impurity concentration of the silicon carbide drift layer; a pair of second well regions provided adjacent to bottom faces of the first well regions, separated by distance W2 larger than the distance W1 by 0.8 ?m or more, and having p-type impurity concentration higher than n-type impurity concentration of the silicon carbide drift layer from 1.1 times to 4.2 times lower than the first well regions; and a highly concentrated JFET region provided between the pair of first well regions and between the pair of second well regions and having n-type impurity concentration higher than that of the silicon carbide drift layer and lower than p-type impurity concentration or the second well regions.

Abstract: A silicon carbide semiconductor device includes a silicon carbide semiconductor substrate having an n-type drift layer, and a p-type well region formed in a surface portion of a part of the drift layer, an insulating film provided on the well region, a gate built-in resistor formed of polysilicon in contact with a surface of the insulating film, an interlayer insulating film formed on the gate built-in resistor, a gate contact wire that is connected to a gate pad and formed on the interlayer insulating film, a gate wire provided on the interlayer insulating layer so as to be apart from the gate contact wire, a first gate contact for electrically connecting the gate contact wire and the gate built-in resistor, and a second gate contact for electrically connecting the gate wire and the gate built-in resistor.

Abstract: A silicon carbide semiconductor device includes: a pair of first well regions separated by distance W1 in surface layer portions of a silicon carbide drift layer and having p-type impurity concentration higher than n-type impurity concentration of the silicon carbide drift layer; a pair of second well regions provided adjacent to bottom faces of the first well regions, separated by distance W2 larger than the distance W1 by 0.8 ?m or more, and having p-type impurity concentration higher than n-type impurity concentration of the silicon carbide drift layer from 1.1 times to 4.2 times lower than the first well regions; and a highly concentrated JFET region provided between the pair of first well regions and between the pair of second well regions and having n-type impurity concentration higher than that of the silicon carbide drift layer and lower than p-type impurity concentration or the second well regions.

Abstract: A method of manufacturing a silicon carbide semiconductor device is provided. The method suppresses the increase in the number of manufacturing steps and is capable of suppressing the degradation of ohmic characteristics of an alloy layer with respect to a semiconductor substrate. The method includes a step of forming a metal layer made of a first metal on a semiconductor substrate made of silicon carbide; a step of forming a metal nitride film obtained by nitriding a second metal on the metal layer; a step of directing a laser light through the metal nitride film to form a layer of an alloy of silicon carbide in the semiconductor substrate and the first metal in the metal layer; and a step of forming an electrode on the metal nitride film.

Abstract: A silicon carbide semiconductor device capable of achieving a decrease in ON resistance and an increase in breakdown voltage and a method for manufacturing a silicon carbide semiconductor device. A silicon carbide semiconductor device includes a silicon carbide substrate and a drift layer. The drift layer includes a breakdown voltage holding layer extending from a point where a doping concentration has a predetermined value to a surface of the drift layer. The doping concentration in the breakdown voltage holding layer continuously decreases from the point where the doping concentration has the predetermined value to a modulation point located further toward the surface of the drift layer than a midpoint in a film thickness direction of the breakdown voltage holding layer. The doping concentration in the breakdown voltage holding layer continuously increases from the modulation point to the surface of the drift layer.

Abstract: A method of manufacturing a silicon carbide semiconductor device is provided. The method suppresses the increase in the number of manufacturing steps and is capable of suppressing the degradation of ohmic characteristics of an alloy layer with respect to a semiconductor substrate. The method includes a step of forming a metal layer made of a first metal on a semiconductor substrate made of silicon carbide; a step of forming a metal nitride film obtained by nitriding a second metal on the metal layer; a step of directing a laser light through the metal nitride film to form a layer of an alloy of silicon carbide in the semiconductor substrate and the first metal in the metal layer; and a step of forming an electrode on the metal nitride film.

Abstract: A silicon carbide semiconductor device capable of achieving a decrease in ON resistance and an increase in breakdown voltage and a method for manufacturing a silicon carbide semiconductor device. A silicon carbide semiconductor device includes a silicon carbide substrate and a drift layer. The drift layer includes a breakdown voltage holding layer extending from a point where a doping concentration has a predetermined value to a surface of the drift layer. The doping concentration in the breakdown voltage holding layer continuously decreases from the point where the doping concentration has the predetermined value to a modulation point located further toward the surface of the drift layer than a midpoint in a film thickness direction of the breakdown voltage holding layer. The doping concentration in the breakdown voltage holding layer continuously increases from the modulation point to the surface of the drift layer.

Abstract: A silicon carbide semiconductor device capable of decreasing an ON-state resistance and improving a breakdown voltage. The silicon carbide semiconductor device includes: a drift layer of a first conductivity type made of a silicon carbide semiconductor; a depletion suppression layer of the first conductivity type formed on the drift layer and having a first conductivity type impurity concentration higher than that of the drift layer; a body region of a second conductivity type formed on the depletion suppression layer; a trench extending through the body region and the depletion suppression layer to reach the drift layer; and a gate insulation film formed along bottom and side surfaces of the trench. The depletion suppression layer has a thickness equal to or greater than 0.06 ?m and equal to or less than 0.31 ?m.