Abstract: A semiconductor device is manufactured by using an SOI substrate having an insulating layer on a substrate and a semiconductor layer on the insulating layer. The semiconductor device is provided with a gate electrode formed on the semiconductor layer via a gate insulating film, a sidewall spacer formed on a sidewall of the gate electrode, a semiconductor layer for source/drain that is epitaxially grown on the semiconductor layer, and a sidewall spacer formed on a sidewall of the semiconductor layer.

Abstract: A semiconductor device is manufactured by using an SOI substrate having an insulating layer on a substrate and a semiconductor layer on the insulating layer. The semiconductor device is provided with a gate electrode formed on the semiconductor layer via a gate insulating film, a sidewall spacer formed on a sidewall of the gate electrode, a semiconductor layer for source/drain that is epitaxially grown on the semiconductor layer, and a sidewall spacer formed on a sidewall of the semiconductor layer.

Abstract: Disclosed is method of manufacturing a semiconductor device. The method includes: forming an insulating film on one side of a substrate; forming a carbon film on the insulating film formed in the forming of the insulating film; forming an insulating film-carbon film laminate including a plurality of insulating films and carbon films alternately laminated on the one side of the substrate, by repeating the forming of the insulating film and the forming of the carbon film multiple times; removing the carbon films included in the insulating film-carbon film laminate; and forming electrode films in regions from which the carbon films are removed in the removing of the carbon films to obtain an insulating film-electrode film laminate in which the insulating films and the electrode films are laminated in a plurality of layers.

Abstract: Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented. A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.

Abstract: The semiconductor device has a gate electrode GE formed on a substrate via a gate insulating film GI and a source/drain semiconductor layer EP1 formed on the substrate. The upper surface of the semiconductor layer EP1 is positioned higher than the upper surface of the substrate straight below the gate electrode GE. And, end parts of the gate electrode GE in a gate length direction are positioned on the semiconductor layer EP1.

Abstract: Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented. A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.

Abstract: A semiconductor device having an n channel MISFET formed on an SOI substrate including a support substrate, an insulating layer formed on the support substrate and a silicon layer formed on the insulating layer has the following structure. An impurity region for threshold adjustment is provided in the support substrate of a gate electrode so that the silicon layer contains carbon. The threshold value can be adjusted by the semiconductor region for threshold adjustment in this manner. Further, by providing the silicon layer containing carbon, even when the impurity of the semiconductor region for threshold adjustment is diffused to the silicon layer across the insulating layer, the impurity is inactivated by the carbon implanted into the silicon layer. As a result, the fluctuation of the transistor characteristics, for example, the fluctuation of the threshold voltage of the MISFET can be reduced.

Abstract: A semiconductor device is manufactured by using an SOI substrate having an insulating layer on a substrate and a semiconductor layer on the insulating layer. The semiconductor device is provided with a gate electrode formed on the semiconductor layer via a gate insulating film, a sidewall spacer formed on a sidewall of the gate electrode, a semiconductor layer for source/drain that is epitaxially grown on the semiconductor layer, and a sidewall spacer formed on a sidewall of the semiconductor layer.

Abstract: Provided are a semiconductor device making it possible to form an element region having a dimension close to a designed dimension, restrain a phenomenon similar to gate-induced drain leakage, and further restrain compressive stress to be applied to the element region by oxidation of a conductive film; and a method for manufacturing the semiconductor device. Trenches are made in a main surface of a semiconductor substrate. By oxidizing the wall surface of each of the trenches, a first oxide film is formed on the wall surface. An embedded conductive film is formed to be embedded into the trench. The embedded conductive film is oxidized in an atmosphere containing an active oxidizing species, thereby forming a second oxide film. A third oxide film is formed on the second oxide film by CVD or coating method.

Abstract: On a semiconductor substrate having an SOI region and a bulk silicon region formed on its upper surface, epitaxial layers are formed in source and drain regions of a MOSFET formed in the SOI region, and no epitaxial layer is formed in source and drain regions of a MOSFET formed in the bulk silicon region. By covering the end portions of the epitaxial layers with silicon nitride films, even when diffusion layers are formed by implanting ions from above the epitaxial layers, it is possible to prevent the impurity ions from being implanted down to a lower surface of a silicon layer.

Abstract: Provided are a semiconductor device making it possible to form an element region having a dimension close to a designed dimension, restrain a phenomenon similar to gate-induced drain leakage, and further restrain compressive stress to be applied to the element region by oxidation of a conductive film; and a method for manufacturing the semiconductor device. Trenches are made in a main surface of a semiconductor substrate. By oxidizing the wall surface of each of the trenches, a first oxide film is formed on the wall surface. An embedded conductive film is formed to be embedded into the trench. The embedded conductive film is oxidized in an atmosphere containing an active oxidizing species, thereby forming a second oxide film. A third oxide film is formed on the second oxide film by CVD or coating method.

Abstract: First bird's beaks are respectively formed in first thermal oxide films at the bottom surface ends and the upper surface ends of a floating gate. In addition, second bird's beaks are formed in second thermal oxide films at the bottom surface ends of a control gate. The dimension of the first thermal oxide films in a gate length direction is smaller than the dimension of the second thermal oxide films in the gate length direction. The first bird's beaks are smaller than the second bird's beaks. In addition, the first bird's beaks are smaller than third bird's beaks (FIG. 12) which are formed in third thermal oxide films at the bottom surface ends of the gate electrode (polysilicon film) of a transistor for a peripheral circuit.

Abstract: A storage node in a capacitor of a semiconductor device is formed of: an inner conductor in a columnar form having bottom, side and top surfaces; and an outer conductor, located on the bottom (between the bottom surface and the semiconductor substrate), side and top surfaces of the inner conductor, having a different material from that of the inner conductor. The outer conductor is formed of a metal film such as of Ru having a film thickness of about 40 nm to 80 nm. The inner conductor is formed of a film, such as a TiN film, a TaN film, a WN film or the like, having a high adhesion to the metal film such as of Ru. With this configuration, it is possible to provide a semiconductor device provided with a capacitor of which the capacitance is obtained.

Abstract: A plurality of capacitors of which the sidewalls, that are storage nodes, extend in the vertical direction are aligned in the horizontal direction. Storage node has a rectangular form made of longer sides and shorter sides in the plan view. A long side of storage node extends, in the plan view, in the direction in which a line extends connecting a first storage node contact and a second storage node contact that is positioned diagonally adjacent to first storage node contact. According to the invention, the capacitance of a memory capacitor is increased.

Abstract: A plurality of capacitors of which the sidewalls, that are storage nodes, extend in the vertical direction are aligned in the horizontal direction. Storage node has a rectangular form made of longer sides and shorter sides in the plan view. A long side of storage node extends, in the plan view, in the direction in which a line extends connecting a first storage node contact and a second storage node contact that is positioned diagonally adjacent to first storage node contact. According to the invention, the capacitance of a memory capacitor is increased.