Abstract: A re-calculator circuit obtains the MCR value of each connection stored in an MCR storage unit, and performs a calculation in such a way as to impartially distribute the available rate band of a FIFO among active connections. The re-calculator circuit stores a rate band attached to the MCR value of each active connection by this calculation, in a virtual MCR storing unit as a virtual MCR value. This rate measurement unit refers to the virtual MCR value stored in the virtual MCR storage unit, and judges whether or not the input cell rate of each active connection exceeds the virtual MCR value. This result is inputted to an input control unit. The input control unit examines the input cell rate information and congestion monitoring information inputted from a queue length monitor unit for monitoring the volume of cells buffered in the FIFO, and determines whether to discard the incoming cell or to input the cell to the FIFO.

Abstract: The present invention relates to a buffer control apparatus and method.

Abstract: According to the present invention, when a current system is switched to a spare system in a transmission system in an asynchronous transfer mode, empty cells transmitted in the current and spare systems are detected, and thereby a timing for switching the current system to the spare system is determined. When no phase difference is existent between the current and spare systems, an empty cell is detected in both the current and spare systems at the same time. Therefore, the current system is switched to the spare system, when an empty cell is detected in both the current and spare systems at the same time. When a shade difference is existent, if an empty cell is detected either in the current or spare systems, another empty cell is inserted in to the systems. Then, the data of the empty cell in a spare system is saved. After the empty cell in a current system passes, the current system is switched to the spare system.

Abstract: A synchronous circuit includes a first circuit block operating in synchronism with a first clock signal, and a second circuit block operating in synchronism with a second clock signal having a frequency lower than that of the first clock signal. The first circuit block includes a frame synchronizing circuit for detecting a synchronous pattern contained in input data having a frame format having a supervisory control data part and an information part, the supervisory control data part including pointer information indicative of a beginning of the information part. The first circuit block includes a synchronizing unit for generating, from the synchronous pattern, a synchronizing control signal for synchronizing the operation of the second circuit block with the operation of the first circuit block. The first circuit block includes a pulse generator for generating a first frame pulse signal from the first clock signal.

Abstract: A phase matching circuit for realizing accurate data transmission and reception through phase shift control only during a data invalid region.

Abstract: A phase adjusting circuit for adjusting a phase of each bit of serial data by synchronizing with a system clock. The phase adjusting circuit includes a plurality of registers. Each bit of data is input into a corresponding one of the plurality of registers in a predetermined cyclic order, synchronized with a receiving clock which is extracted from the data, and outputting outputs of the registers in parallel. The outputs are each selected in a selector circuit under a control of the selector control signal in the same order as the above input to the registers. The selector control signal is generated by detecting a phase relationship between phases of the receiving clock and the system clock, and generating a selector control signal having a phase which is determined according to the phase relationship. Then, each bit of the above selected output is synchronized with the system clock.

Abstract: A reception processing unit receives digital data in successive data frames, each frame comprising a supervisory data field and an associated information data field and, further, a negative stuff or a positive stuff in accordance with need, and detects the head position of the information data field. An enable signal is produced only during and throughout a time interval in which the information data field appears in each successive, received data frame; a count operation of a counter is performed only during the interval of the enable signal. The head position is detected each time the counter finishes counting a number of bytes equal to the fixed length of the information data field.