Patents by Inventor Takaaki Yazawa

Takaaki Yazawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9060456
    Abstract: Multilayer printed wiring boards may be prepared by forming a via hole by laser irradiation in insulating layer formed by a prepreg, comprised of a glass cloth impregnated with a thermosetting resin composition, and subjecting the via hole to a glass etching treatment with a glass etching solution and then to a desmear treatment with an oxidizing agent solution. By such a process, etch back phenomenon and excessive protrusion of glass cloth from the wall surface of a via hole can be sufficiently suppressed, and a highly reliable via can be formed. Particularly, a highly reliable via can be formed in a small via hole having a top diameter of 75 ?m or below.
    Type: Grant
    Filed: August 7, 2013
    Date of Patent: June 16, 2015
    Assignees: AJINOMOTO CO., INC., SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Seiichiro Ohashi, Eiichi Hayashi, Shigeo Nakamura, Takaaki Yazawa, Junichi Nakamura
  • Publication number: 20130319749
    Abstract: Multilayer printed wiring boards may be prepared by forming a via hole by laser irradiation in insulating layer formed by a prepreg, comprised of a glass cloth impregnated with a thermosetting resin composition, and subjecting the via hole to a glass etching treatment with a glass etching solution and then to a desmear treatment with an oxidizing agent solution. By such a process, etch back phenomenon and excessive protrusion of glass cloth from the wall surface of a via hole can be sufficiently suppressed, and a highly reliable via can be formed. Particularly, a highly reliable via can be formed in a small via hole having a top diameter of 75 ?m or below.
    Type: Application
    Filed: August 7, 2013
    Publication date: December 5, 2013
    Applicants: SHINKO ELECTRIC INDUSTRIES CO., LTD., AJINOMOTO CO., INC.
    Inventors: Seiichiro OHASHI, Eiichi Hayashi, Shigeo Nakamura, Takaaki Yazawa, Junichi Nakamura
  • Patent number: 8533942
    Abstract: Multilayer printed wiring boards may be prepared by forming a via hole by laser irradiation in insulating layer formed by a prepreg, comprised of a glass cloth impregnated with a thermosetting resin composition, and subjecting the via hole to a glass etching treatment with a glass etching solution and then to a desmear treatment with an oxidizing agent solution. By such a process, etch back phenomenon and excessive protrusion of glass cloth from the wall surface of a via hole can be sufficiently suppressed, and a highly reliable via can be formed. Particularly, a highly reliable via can be formed in a small via hole having a top diameter of 75 ?m or below.
    Type: Grant
    Filed: November 21, 2008
    Date of Patent: September 17, 2013
    Assignees: Ajinomoto Co., Inc., Shinko Electric Industries Co., Ltd.
    Inventors: Seiichiro Ohashi, Eiichi Hayashi, Shigeo Nakamura, Takaaki Yazawa, Junichi Nakamura
  • Publication number: 20090133910
    Abstract: Multilayer printed wiring boards may be prepared by forming a via hole by laser irradiation in insulating layer formed by a prepreg, comprised of a glass cloth impregnated with a thermosetting resin composition, and subjecting the via hole to a glass etching treatment with a glass etching solution and then to a desmear treatment with an oxidizing agent solution. By such a process, etch back phenomenon and excessive protrusion of glass cloth from the wall surface of a via hole can be sufficiently suppressed, and a highly reliable via can be formed. Particularly, a highly reliable via can be formed in a small via hole having a top diameter of 75 ?m or below.
    Type: Application
    Filed: November 21, 2008
    Publication date: May 28, 2009
    Applicants: AJINOMOTO CO., INC, SHINKO ELECTRIC INDUSTRIES CO.,LTD.
    Inventors: Seiichiro OHASHI, Eiichi Hayashi, Shigeo Nakamura, Takaaki Yazawa, Junichi Nakamura
  • Patent number: 6767616
    Abstract: A metal core substrate comprises a core layer (10) consisting of first and second metal plates (11, 12) layered with a third insulating layer (13) interposed therebetween; first and second insulating layers (20, 21) formed on the first and metal plates, respectively; first and second wiring patterns (45, 46) formed on the first and second insulating layers, respectively. A conductive layer (40) formed in a through-hole (22) penetrates the first insulating layer, the first metal plate, the third insulating layer, the second metal plate and the second insulating layer for electrically connecting the first wiring pattern with the second wiring pattern. The first metal plate (11) is electrically connected with the first wiring pattern (45) and the second wiring pattern (46), respectively, by means of a via (44) and by means a via (43).
    Type: Grant
    Filed: May 13, 2003
    Date of Patent: July 27, 2004
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Kazuhiko Ooi, Masaru Yamazaki, Yukiji Watanabe, Takaaki Yazawa
  • Publication number: 20030215619
    Abstract: A metal core substrate comprises a core layer (10) consisting of first and second metal plates (11, 12) layered with a third insulating layer (13) interposed therebetween; first and second insulating layers (20, 21) formed on the first and metal plates, respectively; first and second wiring patterns (45, 46) formed on the first and second insulating layers, respectively. A conductive layer (40) formed in a through-hole (22) penetrates the first insulating layer, the first metal plate, the third insulating layer, the second metal plate and the second insulating layer for electrically connecting the first wiring pattern with the second wiring pattern. The first metal plate (11) is electrically connected with the first wiring pattern (45) and the second wiring pattern (46), respectively, by means of a via (44) and by means a via (43).
    Type: Application
    Filed: May 13, 2003
    Publication date: November 20, 2003
    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Kazuhiko Ooi, Masaru Yamazaki, Yukiji Watanabe, Takaaki Yazawa