Patents by Inventor Takaco UMEZAWA

Takaco UMEZAWA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240038662
    Abstract: A semiconductor device includes a first wiring extending in a first direction and a second wiring extending in a second direction crossing the first direction and having an end that faces the first wiring and is a predetermined distance away from the first wiring. The predetermined distance is approximately equal to a width of the second wiring, and the end of the second wiring is formed into one or more loops.
    Type: Application
    Filed: October 6, 2023
    Publication date: February 1, 2024
    Inventor: Takaco UMEZAWA
  • Patent number: 11824003
    Abstract: A semiconductor device includes a first wiring extending in a first direction and a second wiring extending in a second direction crossing the first direction and having an end that faces the first wiring and is a predetermined distance away from the first wiring. The predetermined distance is approximately equal to a width of the second wiring, and the end of the second wiring is formed into one or more loops.
    Type: Grant
    Filed: November 24, 2020
    Date of Patent: November 21, 2023
    Assignee: Kioxia Corporation
    Inventor: Takaco Umezawa
  • Patent number: 11805635
    Abstract: According to one embodiment, a semiconductor memory device includes, on a substrate, a memory region and a peripheral circuit region in which an MOS transistor is formed. The MOS transistor includes a drain region and a source region disposed in a first direction parallel to a surface of the substrate. On a surface of the drain region, a drain electrode is formed to be connected with a contact plug. Further, on a surface of the source region, a source electrode is formed to be connected with a contact plug. When viewed in the first direction, the drain electrode has a region that does not overlap with the source electrode, and the source electrode has a region that does not overlap with the drain electrode.
    Type: Grant
    Filed: August 13, 2020
    Date of Patent: October 31, 2023
    Assignee: Kioxia Corporation
    Inventors: Hiroaki Yamamoto, Shinichi Asou, Kenichi Kawabata, Haruyuki Miyata, Takahiro Shimokawa, Takaco Umezawa, Syunsuke Sasaki
  • Publication number: 20220189868
    Abstract: A semiconductor storage device includes a first signal line extending in a first direction, and second signal line extending in the first direction and adjacent to the first signal line in a second direction orthogonal to the first direction. The first signal line includes a trunk wiring extending in the first direction, and one or more branch wirings branched from the trunk wiring and extending on one side toward the second signal line in the second direction.
    Type: Application
    Filed: August 26, 2021
    Publication date: June 16, 2022
    Inventors: Takaco UMEZAWA, Hiroaki YAMAMOTO, Shinichi ASOU, Tetsuya TADA, Katsuaki MOURI, Takahiro SHIMOKAWA, Syunsuke SASAKI
  • Publication number: 20210280587
    Abstract: According to one embodiment, a semiconductor memory device includes, on a substrate, a memory region 600 and a peripheral circuit region 500 in which an MOS transistor 100 is formed. The MOS transistor 100 includes a drain region 120 and a source region 130 disposed in a first direction parallel to a surface of the substrate. On a surface of the drain region 120, a drain electrode 121 is formed to be connected with a contact plug 122. Further, on a surface of the source region 130, a source electrode 131 is formed to be connected with a contact plug 132. When viewed in the first direction, the drain electrode 121 has a region that does not overlap with the source electrode 131, and the source electrode 131 has a region that does not overlap with the drain electrode 121.
    Type: Application
    Filed: August 13, 2020
    Publication date: September 9, 2021
    Applicant: Kioxia Corporation
    Inventors: Hiroaki YAMAMOTO, Shinichi Asou, Kenichi Kawabata, Haruyuki Miyata, Takahiro Shimokawa, Takaco Umezawa, Syunsuke Sasaki
  • Publication number: 20210074637
    Abstract: A semiconductor device includes a first wiring extending in a first direction and a second wiring extending in a second direction crossing the first direction and having an end that faces the first wiring and is a predetermined distance away from the first wiring. The predetermined distance is approximately equal to a width of the second wiring, and the end of the second wiring is formed into one or more loops.
    Type: Application
    Filed: November 24, 2020
    Publication date: March 11, 2021
    Inventor: Takaco UMEZAWA
  • Patent number: 10886221
    Abstract: A semiconductor device includes a first wiring extending in a first direction and a second wiring extending in a second direction crossing the first direction and having an end that faces the first wiring and is a predetermined distance away from the first wiring. The predetermined distance is approximately equal to a width of the second wiring, and the end of the second wiring is formed into one or more loops.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: January 5, 2021
    Assignee: Toshiba Memory Corporation
    Inventor: Takaco Umezawa
  • Publication number: 20200091069
    Abstract: A semiconductor device includes a first wiring extending in a first direction and a second wiring extending in a second direction crossing the first direction and having an end that faces the first wiring and is a predetermined distance away from the first wiring. The predetermined distance is approximately equal to a width of the second wiring, and the end of the second wiring is formed into one or more loops.
    Type: Application
    Filed: February 26, 2019
    Publication date: March 19, 2020
    Inventor: Takaco UMEZAWA