Patents by Inventor Takae Sakai

Takae Sakai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9230924
    Abstract: In order to securely ground an exterior shield and reduce burden imposed on a dicing blade and the exterior shield, a method of producing a semiconductor module comprises a hole-forming step of forming a hole 30 extending from a top surface of a sealing resin layer 3 to a ground wiring 111 (112) provided at a collective substrate 100, a film-forming step of forming an electrically conductive film made of an electrically conductive material so as to cover at least the top surface of the sealing resin layer 3, an internal surface of the hole 20, and the ground wiring 111 (112), and a separation step of separating from each other a plurality of individual module sections which the individual module section comprises.
    Type: Grant
    Filed: June 2, 2015
    Date of Patent: January 5, 2016
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Takae Sakai, Masahiro Murakami, Masahiko Kushino, Yoshihisa Amano, Shinichi Tokuno
  • Publication number: 20150303155
    Abstract: In order to securely ground an exterior shield and reduce burden imposed on a dicing blade and the exterior shield, a method of producing a semiconductor module comprises a hole-forming step of forming a hole 30 extending from a top surface of a sealing resin layer 3 to a ground wiring 111 (112) provided at a collective substrate 100, a film-forming step of forming an electrically conductive film made of an electrically conductive material so as to cover at least the top surface of the sealing resin layer 3, an internal surface of the hole 20, and the ground wiring 111 (112), and a separation step of separating from each other a plurality of individual module sections which the individual module section comprises.
    Type: Application
    Filed: June 2, 2015
    Publication date: October 22, 2015
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Takae SAKAI, Masahiro MURAKAMI, Masahiko KUSHINO, Yoshihisa AMANO, Shinichi TOKUNO
  • Patent number: 9076892
    Abstract: In order to securely ground an exterior shield and reduce burden imposed on a dicing blade and the exterior shield, a method of producing a semiconductor module comprises a hole-forming step of forming a hole 30 extending from a top surface of a sealing resin layer 3 to a ground wiring 111 (112) provided at a collective substrate 100, a film-forming step of forming an electrically conductive film made of an electrically conductive material so as to cover at least the top surface of the sealing resin layer 3, an internal surface of the hole 20, and the ground wiring 111 (112), and a separation step of separating from each other a plurality of individual module sections which the individual module section comprises.
    Type: Grant
    Filed: May 11, 2012
    Date of Patent: July 7, 2015
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Takae Sakai, Masahiro Murakami, Masahiko Kushino, Yoshihisa Amano, Shinichi Tokuno
  • Patent number: 8320502
    Abstract: A digital demodulating apparatus comprises circuit components constituting a tuner that applies channel select processing to a received signal, and a demodulator that demodulates the signal to which the tuner has applied channel select processing; a power supply unit that supplies power to each circuit component; a reception condition detecting unit that detects a reception condition when the tuner receives the signal; a power adjusting unit that adjusts the power to be supplied to each circuit component by the power supply unit, on the basis of a result of the detection by the reception condition detecting unit; a fading environment estimating unit that estimates a fading environment when the tuner receives the signal; and a power controlling unit that controls the power adjusting unit on the basis of a result of the estimation by the fading environment estimating unit so that the number of times of adjustments of the power by the power adjusting unit per unit time changes in accordance with the variability
    Type: Grant
    Filed: May 6, 2008
    Date of Patent: November 27, 2012
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Takae Sakai, Nobuyoshi Kaiki
  • Publication number: 20120286415
    Abstract: In order to securely ground an exterior shield and reduce burden imposed on a dicing blade and the exterior shield, a method of producing a semiconductor module comprises a hole-forming step of forming a hole 30 extending from a top surface of a sealing resin layer 3 to a ground wiring 111 (112) provided at a collective substrate 100, a film-forming step of forming an electrically conductive film made of an electrically conductive material so as to cover at least the top surface of the sealing resin layer 3, an internal surface of the hole 20, and the ground wiring 111 (112), and a separation step of separating from each other a plurality of individual module sections which the individual module section comprises.
    Type: Application
    Filed: May 11, 2012
    Publication date: November 15, 2012
    Inventors: Takae Sakai, Masahiro Murakami, Masahiko Kushino, Yoshihisa Amano, Shinichi Tokuno
  • Patent number: 7881672
    Abstract: A digital demodulating apparatus comprises a tuner constituted by circuit elements to perform channel select processing to a signal; a demodulator that performs demodulation processing to a signal output from the tuner; a power supply unit that supplies a normal power to each circuit element, and supplies to the circuit element a test power different from the normal power, over a first time period in place of the normal power; a test noise measuring unit that measures the intensity of test noise contained in a signal to be output from the tuner, when the power supply unit supplies the test power over the first time period; a comparing unit that compares the intensity of the test noise measured by the test noise measuring unit with a noise reference value as a reference for updating of the normal power; and a power updating unit that updates the intensity of the normal power on the basis of a result of the comparison by the comparing unit.
    Type: Grant
    Filed: January 18, 2007
    Date of Patent: February 1, 2011
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Nobuyoshi Kaiki, Takae Sakai, Masayuki Natsumi, Kazumasa Kioi
  • Patent number: 7796962
    Abstract: A digital demodulating apparatus includes a tuner that selectively receives one of frequency bands, and a demodulator that demodulates a signal from the tuner.
    Type: Grant
    Filed: July 6, 2007
    Date of Patent: September 14, 2010
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Takae Sakai, Nobuyoshi Kaiki
  • Publication number: 20090041158
    Abstract: A digital demodulating apparatus comprises circuit components constituting a tuner that applies channel select processing to a received signal, and a demodulator that demodulates the signal to which the tuner has applied channel select processing; a power supply unit that supplies power to each circuit component; a reception condition detecting unit that detects a reception condition when the tuner receives the signal; a power adjusting unit that adjusts the power to be supplied to each circuit component by the power supply unit, on the basis of a result of the detection by the reception condition detecting unit; a fading environment estimating unit that estimates a fading environment when the tuner receives the signal; and a power controlling unit that controls the power adjusting unit on the basis of a result of the estimation by the fading environment estimating unit so that the number of times of adjustments of the power by the power adjusting unit per unit time changes in accordance with the variability
    Type: Application
    Filed: May 6, 2008
    Publication date: February 12, 2009
    Inventors: Takae SAKAI, Nobuyoshi Kaiki
  • Publication number: 20080130455
    Abstract: A digital demodulating apparatus includes a supplying unit that supplies power to each of circuit elements constituting a receiving unit that receives a signal, and a demodulating unit that demodulates the received signal. The apparatus further includes a correcting unit that corrects errors due to noises generated on a transmission path of the received signal; a calculating unit that calculates a value indicating the quantity of noises contained in the signal when the correcting unit corrects the errors; a judging unit that judges whether or not reception conditions of the received signal are good in a predetermined time period, based on values calculated by the calculating unit; and a reducing unit that reduces the power to be supplied to each circuit element by the supplying unit, when the judging unit decides that the reception conditions are good.
    Type: Application
    Filed: August 9, 2007
    Publication date: June 5, 2008
    Inventors: Nobuyoshi Kaiki, Takae Sakai
  • Publication number: 20080074556
    Abstract: A digital demodulating apparatus includes a tuner that selectively receives one of frequency bands, and a demodulator that demodulates a signal from the tuner.
    Type: Application
    Filed: July 6, 2007
    Publication date: March 27, 2008
    Inventors: Takae Sakai, Nobuyoshi Kaiki
  • Publication number: 20070275680
    Abstract: A digital demodulating apparatus comprises a tuner constituted by circuit elements to perform channel select processing to a signal; a demodulator that performs demodulation processing to a signal output from the tuner; a power supply unit that supplies a normal power to each circuit element, and supplies to the circuit element a test power different from the normal power, over a first time period in place of the normal power; a test noise measuring unit that measures the intensity of test noise contained in a signal to be output from the tuner, when the power supply unit supplies the test power over the first time period; a comparing unit that compares the intensity of the test noise measured by the test noise measuring unit with a noise reference value as a reference for updating of the normal power; and a power updating unit that updates the intensity of the normal power on the basis of a result of the comparison by the comparing unit.
    Type: Application
    Filed: January 18, 2007
    Publication date: November 29, 2007
    Inventors: Nobuyoshi Kaiki, Takae Sakai, Masayuki Natsumi, Kazumasa Kioi