Abstract: Disclosed is a HOUT position control circuit used to control the horizontal position of display image in a multisync monitor. The circuit has: a first PLL circuit that is phase-locked with input horizontal synchronous signal; a second PLL circuit that is phase-locked with output of the first PLL circuit; and a circuit for generating a delay between outputs of the first PLL circuit and the second PLL circuit to control the delay amount from the input horizontal synchronous signal to output horizontal drive signal.

Abstract: There is disclosed a phase-locked loop (PLL) circuit for use in an improved deflection correction circuit for a larger and flat display device. The PLL circuit has a phase comparator circuit, a filter, and a voltage-controlled oscillator (VCO) connected in series in this order. The output signal from the VCO is fed back to the phase comparator circuit. The PLL circuit further includes a period-detecting circuit for detecting the period of an externally applied signal and a frequency divider circuit. This frequency divider circuit divides the frequency of the output signal from the VCO according to the period detected by the period-detecting circuit and feeds the resulting signal back to the VCO.

Abstract: In a digital/analog converter for (m+n)-bit, digital input data, a sigma-delta type pulse modulation circuit receives lower-order n bits of the digital input data to generate 1-bit data corresponding to the lower-order n bits in synchronization with a clock signal. An m-bit adder adds the 1-bit data to upper-order m bits of the digital input data. An m-bit digital/analog conversion section performs a digital-to-analog conversion upon an output value of the m-bit adder. A low-pass filter removes a high frequency component of an output value of the m-bit digital/analog conversion section to generate an analog data corresponding to the (m+n)-bit digital input data.

Abstract: A digital PLL circuit is formed by a first digital PLL circuit, a signal generation circuit that generates a plurality of signals that have the same frequency as the output of the first PLL circuit but differing phases, and the second digital PLL circuit having a signal selecting circuit that can select the signals from the signal generation circuit, a frequency divider circuit that divides the output signal of the signal selecting circuit, a phase comparator circuit that compares the phase between the a signal used as a reference and the output signal from the frequency divider circuit, an up/down counter that detects the phase difference of the phase comparison circuit, and a digital filter that is provided between the up/down counter and the signal selecting circuit, the second PLL circuit selecting the signals from the signal generation circuit based on the output from the up/down counter.

Abstract: A phase locked loop makes a system clock signal synchronous to a horizontal synchronizing signal for a display unit, and a lock-in detecting circuit monitors said phase locked loop to see whether or not a phase difference takes place between the system clock signal and the horizontal synchronizing signal, wherein the lock-in detecting circuit measures the unlocked state between the system clock signal and the horizontal synchronizing signal in a window defined in a vertical synchronizing period and, thereafter, compares the time period of the unlocked state with a critical value to see whether or not the unlocked state is due to a temporary phenomenon or a phase difference to be corrected so that an detecting signal of the lock-in detecting circuit is reliable.

Abstract: An OSD clock generating circuit includes a PPL circuit controlled to oscillate to generate an OSD clock signal phase-locked with a level transition point of a horizontal synchronous signal. When an OSD device is used in a multisync monitor capable of changing its horizontal synchronous signal frequency, an OSD data can be displayed with the same size without being influenced by a change of the frequency of the horizontal synchronous signal.

Abstract: Disclosed is a composite video generator comprising a color signal generating means, a color selecting means and an output means, and further being provided with a color change detecting means and a low amplitude color signal generating means. The composite video signal generator which combines a composite video input signal with a color signal as a character signal in accordance with a character data presence/absence signal to output the resultant signal as a composite video output signal. The composite video signal generator detects changes in the color signal and character data presence/absence signal and lowers the amplitude of the color signal at each change point, thereby suppressing the occurrence of a dot disturbance and color mixture.