Patents by Inventor Takafumi Kamimura

Takafumi Kamimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • GA2O3-based semiconductor device
    Patent number: 11563092
    Abstract: A Ga2O3-based semiconductor device includes a Ga2O3-based crystal layer including a donor, and an N-doped region formed in at least a part of the Ga2O3-based crystal layer.
    Type: Grant
    Filed: April 26, 2018
    Date of Patent: January 24, 2023
    Assignees: National Institute of Information and Communications Technology, Tamura Corporation, Novel Crystal Technology, Inc
    Inventors: Masataka Higashiwaki, Yoshiaki Nakata, Takafumi Kamimura, Man Hoi Wong, Kohei Sasaki, Daiki Wakimoto
  • GA2O3-BASED SEMICONDUCTOR DEVICE
    Publication number: 20200144377
    Abstract: A Ga2O3-based semiconductor device includes a Ga2O3-based crystal layer including a donor, and an N-doped region formed in at least a part of the Ga2O3-based crystal layer.
    Type: Application
    Filed: April 26, 2018
    Publication date: May 7, 2020
    Applicants: NATIONAL INSTITUTE OF INFORMATION AND COMMUNICATIONS TECHNOLOGY, TAMURA CORPORATION, NOVEL CRYSTAL TECHNOLOGY, INC.
    Inventors: Masataka HIGASHIWAKI, Yoshiaki NAKATA, Takafumi KAMIMURA, Man Hoi WONG, Kohei SASAKI, Daiki WAKIMOTO
  • Memory device with reduced programming voltage method of reduction of programming voltage and method of reading such memory device
    Patent number: 8223548
    Abstract: A memory device (1) includes at least a first semiconductor region (100) having a length, a first surface, and a cross section surrounded by the first surface, a memory means (300) provided on the first surface, and a gate (400) provided on the memory means (300), and an equivalent sectional radius of the cross section of the first semiconductor region (100) is set to be equal to or smaller than an equivalent silicon oxide film thickness of the memory means (300) to realize low program voltage. The equivalent sectional radius r of the cross section is set to be 10 nm or less and the gate length is set to be 20 nm or less so that multi-level interval converted to gate voltage becomes a specific value which can be identified under the room temperature.
    Type: Grant
    Filed: May 23, 2008
    Date of Patent: July 17, 2012
    Assignee: National Institute of Advanced Industrial Science and Technology
    Inventors: Yutaka Hayashi, Kazuhiko Matsumoto, Takafumi Kamimura
  • MEMORY DEVICE AND READING METHOD THEREOF
    Publication number: 20100208522
    Abstract: A memory device (1) includes at least a first semiconductor region (100) having a length, a first surface, and a cross section surrounded by the first surface, a memory means (300) provided on the first surface, and a gate (400) provided on the memory means (300), and an equivalent sectional radius of the cross section of the first semiconductor region (100) is set to be equal to or smaller than an equivalent silicon oxide film thickness of the memory means (300) to realize low program voltage. The equivalent sectional radius r of the cross section is set to be 10 nm or less and the gate length is set to be 20 nm or less so that multi-level interval converted to gate voltage becomes a specific value which can be identified under the room temperature.
    Type: Application
    Filed: May 23, 2008
    Publication date: August 19, 2010
    Inventors: Yutaka Hayashi, Kazuhika Matsumoto, Takafumi Kamimura