Patents by Inventor Takafumi Konno
Takafumi Konno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11674083Abstract: Provided are a thermoplastic polymer capable of reducing a dielectric dissipation factor in high frequency bands and a film thereof. The thermoplastic liquid crystal polymer includes repeating units represented by the following formulae (I), (II), (III) and (IV), in which a molar ratio of a total amount of the repeating units represented by formulae (I) and (II) to a total amount of all the repeating units in the thermoplastic liquid crystal polymer is 50 to 90 mol %, and a molar ratio of the repeating unit represented by formula (III) to the repeating unit represented by formula (IV) is the former/the latter=23/77 to 77/23.Type: GrantFiled: September 20, 2019Date of Patent: June 13, 2023Assignee: KURARAY CO., LTD.Inventors: Takafumi Konno, Tatsuya Sunamoto, Michiyuki Nanba, Tetsuya Hara
-
Patent number: 11429646Abstract: A method includes: determining, based on an elapsed time, a priority for each of groups obtained by clustering a plurality of pieces of response information based on similarity between the pieces of response information, each response information indicating a response to an event that has occurred, the elapsed time being measured from a time period in which the event recorded in each response information of each group occurred most often; calculating credibility for each response information, based on a number of times specifications of a system relating to the event have been changed after the response, and an elapsed time from date and time when the response recorded in the pieces of response information has been made; and controlling a presentation mode upon presenting the plurality of pieces of response information, based on the priority calculated for each group and the credibility calculated for each response information.Type: GrantFiled: December 21, 2020Date of Patent: August 30, 2022Assignee: FUJITSU LIMITEDInventors: Ichiro Kotani, Makoto Adachi, Takashi Maeda, Takafumi Konno, Kazuki Yamada
-
Publication number: 20210240743Abstract: A method includes: determining, based on an elapsed time, a priority for each of groups obtained by clustering a plurality of pieces of response information based on similarity between the pieces of response information, each response information indicating a response to an event that has occurred, the elapsed time being measured from a time period in which the event recorded in each response information of each group occurred most often; calculating credibility for each response information, based on a number of times specifications of a system relating to the event have been changed after the response, and an elapsed time from date and time when the response recorded in the pieces of response information has been made; and controlling a presentation mode upon presenting the plurality of pieces of response information, based on the priority calculated for each group and the credibility calculated for each response information.Type: ApplicationFiled: December 21, 2020Publication date: August 5, 2021Applicant: FUJITSU LIMITEDInventors: Ichiro Kotani, Makoto Adachi, Takashi Maeda, Takafumi Konno, Kazuki Yamada
-
Publication number: 20200017769Abstract: Provided are a thermoplastic polymer capable of reducing a dielectric dissipation factor in high frequency bands and a film thereof. The thermoplastic liquid crystal polymer includes repeating units represented by the following formulae (I), (II), (III) and (IV), in which a molar ratio of a total amount of the repeating units represented by formulae (I) and (II) to a total amount of all the repeating units in the thermoplastic liquid crystal polymer is 50 to 90 mol %, and a molar ratio of the repeating unit represented by formula (III) to the repeating unit represented by formula (IV) is the former/the latter=23/77 to 77/23.Type: ApplicationFiled: September 20, 2019Publication date: January 16, 2020Applicant: Kuraray Co., Ltd.Inventors: Takafumi KONNO, Tatsuya SUNAMOTO, Michiyuki NANBA, Tetsuya HARA
-
Patent number: 9538646Abstract: To provide a thermoplastic liquid crystal polymer film capable of suppressing change in relative dielectric constant before and after heating, and a laminated and a circuit board using the same. In this film, a change ratio of a dielectric constant (?r2) of the film after heating to a dielectric constant (?r1) of the film before the heating satisfies the following formula (I) where the film is heated for 1 hour at a temperature in a range from a temperature being 30° C. lower than a melting point of the film to a temperature being 10° C. higher than the melting point, |?r2??r1|/?r1×100?5??(I) where ?r1 denotes the relative dielectric constant before the heating, ?r2 denotes the relative dielectric constant after the heating. These relative dielectric constants are measured at the same frequency in a range of 1 to 100 GHz.Type: GrantFiled: April 23, 2014Date of Patent: January 3, 2017Assignee: KURARAY CO., LTD.Inventors: Minoru Onodera, Tatsuya Sunamoto, Shuji Matsunaga, Takafumi Konno
-
Publication number: 20150017413Abstract: A thermoplastic liquid polymer film and a method of producing the same are provided. The method includes preparing a thermoplastic liquid crystal polymer film that has dielectric constants of not larger than 3.25 both in an MD direction and in a TD direction; and performing drawing of the film while heating the film at a temperature in a range from a temperature (Td-60° C.) that is 60° C. lower than a heat deformation temperature (Td) of the film to a temperature (Td-5° C.) that is 5° C. lower than Td. The temperature of the heating during the drawing of the film may be in a range from a temperature (Td-40° C.) that is 40° C. lower than a heat deformation temperature (Td) of the film subjected to the drawing to a temperature (Td-10° C.) that is 10° C. lower than Td.Type: ApplicationFiled: September 29, 2014Publication date: January 15, 2015Applicant: KURARAY CO., LTDInventors: Takafumi KONNO, Tatsuya SUNAMOTO, Minoru ONODERA, Shuji MATSUNAGA, Kazuyuki OHMORI
-
Publication number: 20140231123Abstract: To provide a thermoplastic liquid crystal polymer film capable of suppressing change in relative dielectric constant before and after heating, and a laminated and a circuit board using the same. In this film, a change ratio of a dielectric constant (?r2) of the film after heating to a dielectric constant (?r1) of the film before the heating satisfies the following formula (I) where the film is heated for 1 hour at a temperature in a range from a temperature being 30° C. lower than a melting point of the film to a temperature being 10° C. higher than the melting point, |?r2??r1|/?r1×100?5??(I) where ?r1 denotes the relative dielectric constant before the heating, ?r2 denotes the relative dielectric constant after the heating. These relative dielectric constants are measured at the same frequency in a range of 1 to 100 GHz.Type: ApplicationFiled: April 23, 2014Publication date: August 21, 2014Applicant: KURARAY CO., LTD.Inventors: Minoru ONODERA, Tatsuya SUNAMOTO, Shuji MATSUNAGA, Takafumi KONNO
-
Patent number: 8466540Abstract: The reliability of a semiconductor device is prevented from being reduced. A planar shape of a sealing body is comprised of a quadrangle having a pair of first sides, and a pair of second sides crossing with the first sides. Further, it has a die pad, a controller chip (first semiconductor chip) and a sensor chip (second semiconductor chip) mounted over the die pad, and a plurality of leads arranged along the first sides of the sealing body. The controller chip and the leads are electrically coupled to each other via wires (first wires), and the sensor chip and the controller chip are electrically coupled to each other via wires (second wires). Herein, the die pad is supported by a plurality of suspending leads formed integrally with the die pad and extending from the die pad toward the first sides of the sealing body. Each of the suspending leads has an offset part.Type: GrantFiled: January 26, 2010Date of Patent: June 18, 2013Assignee: Renesas Electronics CorporationInventors: Shigeki Tanaka, Masakazu Sakano, Toshiyuki Shinya, Takafumi Konno, Kazuaki Yoshida, Takashi Sato, Atsushi Fujisawa
-
Publication number: 20100193923Abstract: The reliability of a semiconductor device is prevented from being reduced. A planar shape of a sealing body is comprised of a quadrangle having a pair of first sides, and a pair of second sides crossing with the first sides. Further, it has a die pad, a controller chip (first semiconductor chip) and a sensor chip (second semiconductor chip) mounted over the die pad, and a plurality of leads arranged along the first sides of the sealing body. The controller chip and the leads are electrically coupled to each other via wires (first wires), and the sensor chip and the controller chip are electrically coupled to each other via wires (second wires). Herein, the die pad is supported by a plurality of suspending leads formed integrally with the die pad and extending from the die pad toward the first sides of the sealing body. Each of the suspending leads has an offset part.Type: ApplicationFiled: January 26, 2010Publication date: August 5, 2010Applicant: Renesas Technology Corp.Inventors: Shigeki Tanaka, Masakazu Sakano, Toshiyuki Shinya, Takafumi Konno, Kazuaki Yoshida, Takashi Sato, Atsushi Fujisawa
-
Patent number: 6909179Abstract: A semiconductor device includes a substrate, a semiconductor chip mounted on one surface of the substrate, wherein the semiconductor chip has an integrated circuit and bonding pads formed on a main surface thereof. The main surface of the semiconductor chip has a quadrilateral shape with the bonding pads being disposed along four sides of the main surface. A plurality of conductors is disposed on the one surface of the substrate so as to surround the semiconductor chip along four sides thereof and a plurality of bonding wires electrically connect the bonding pads with tips of the conductors, respectively. A resin body seals the semiconductor chip, the conductors and the plurality of bonding wires. A pitch between adjacent bonding pads increases in a direction toward four corners defined by the four sides of the main surface of the semiconductor chip.Type: GrantFiled: July 16, 2001Date of Patent: June 21, 2005Assignees: Renesas Technology Corp., Hitachi Hokkai Semiconductor, Ltd.Inventors: Shigeki Tanaka, Atsushi Fujisawa, Souichi Nagano, Tsugihiko Hirano, Ryouichi Oota, Takafumi Konno, Kenichi Tatebe, Toshiaki Okamoto
-
Patent number: 6887739Abstract: In a method of forming a ball grid array type semiconductor package, a semiconductor chip is mounted through an adhesive material on a surface of a flexible film substrate. Plural bump electrodes are arranged in an array on the opposite side of said substrate and the semiconductor chip is sealed by a resin. In this regard, an insulation layer is formed to cover an electric conductor layer pattern formed on the surface of the substrate, and the semiconductor chip is mounted through an adhesive material on the insulation layer. The insulation layer is divided into a plural number of parts that are mutually discontinuous in the area under the semiconductor chip. By this divided insulation layer, a short circuit between the semiconductor chip and the electric conductor layer pattern is prevented and a deformation of the substrate that comprises the flexible films is suppressed.Type: GrantFiled: July 3, 2003Date of Patent: May 3, 2005Assignees: Renesas Technology Corp., Hitachi Hokkai Semiconductor, Ltd.Inventors: Atsushi Fujisawa, Takafumi Konno, Shingo Ohsaka, Ryo Haruta, Masahiro Ichitani
-
Publication number: 20040262752Abstract: A semiconductor chip has a plurality of electrodes arranged along one side thereof; a plurality of leads arranged outside the one side thereof in the same direction as the above side; a plurality of bonding wires electrically connecting the electrodes to the leads; and a resin sealing member sealing the semiconductor chip, the leads and the bonding wires. The leads include first leads, each having a terminal portion which is located on the side face of the resin sealing member and exposed from the rear surface thereof, and second leads, each having a terminal portion which is located on the inner side of the terminal portions of the first leads and exposed from the rear surface of the resin sealing member. The first leads and the second leads are arranged alternately. The plurality of bonding wires are connected to the respective leads on the inner side of the terminal portions of the first leads.Type: ApplicationFiled: June 4, 2004Publication date: December 30, 2004Inventors: Fujio Ito, Hiromichi Suzuki, Takafumi Konno, Tsugio Umehara
-
Patent number: 6803258Abstract: In a semiconductor device having a heat radiation plate, the tips of inner leads connected to a semiconductor chip have a lead width w and a lead thickness t, the width being less than the thickness. The inner leads are secured to the heat radiation plate. Fastening the inner leads to the heat radiation plate supports the latter and eliminates the need for suspending leads. A lead pitch p, the lead width w and lead thickness t of the inner lead tips connected to the semiconductor chip have the relations of w<t and p≦1.2t, with the inner leads secured to the heat radiation plate. The heat radiation plate has slits made therein to form radially shaped heat propagation paths between a semiconductor chip mounting area and the inner leads.Type: GrantFiled: May 23, 2002Date of Patent: October 12, 2004Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd., Hitachi Hokkai Semiconductor, Ltd.Inventors: Fujio Ito, Hiroaki Tanaka, Hiromichi Suzuki, Tokuji Toida, Takafumi Konno, Kunihiro Tsubosaki, Shigeki Tanaka, Kazunari Suzuki, Akihiko Kameoka
-
Patent number: 6764878Abstract: In a ball grid array type semiconductor package, a semiconductor chip is mounted through an adhesive material on a surface of a flexible film substrate. Plural bump electrodes are arranged in an array on the opposite side of said substrate and the semiconductor chip is sealed by a resin. In this regard, an insulation layer is formed to cover an electric conductor layer pattern formed on the surface of the substrate, and the semiconductor chip is mounted through an adhesive material on the insulation layer. The insulation layer is divided into a plural number of parts that are mutually discontinuous in the area under the semiconductor chip. By this divided insulation layer, a short circuit between the semiconductor chip and the electric conductor layer pattern is prevented and a deformation of the substrate that comprises the flexible films is suppressed.Type: GrantFiled: July 12, 2002Date of Patent: July 20, 2004Assignees: Renesas Technology Corp., Hitachi Hokkai Semiconductor, Ltd.Inventors: Atsushi Fujisawa, Takafumi Konno, Shingo Ohsaka, Ryo Haruta, Masahiro Ichitani
-
Patent number: 6759279Abstract: In a method of forming a ball grid array type semiconductor package, a semiconductor chip is mounted through an adhesive material on a surface of a flexible film substrate. Plural bump electrodes are arranged in an array on the opposite side of said substrate and the semiconductor chip is sealed by a resin. In this regard, an insulation layer is formed to cover an electric conductor layer pattern formed on the surface of the substrate, and the semiconductor chip is mounted through an adhesive material on the insulation layer. The insulation layer is divided into a plural number of parts that are mutually discontinuous in the area under the semiconductor chip. By this divided insulation layer, a short circuit between the semiconductor chip and the electric conductor layer pattern is prevented and a deformation of the substrate that comprises the flexible films is suppressed.Type: GrantFiled: August 8, 2002Date of Patent: July 6, 2004Assignees: Renesas Technology Corp., Hitachi Hokkai Semiconductor, Ltd.Inventors: Atsushi Fujisawa, Takafumi Konno, Shingo Ohsaka, Ryo Haruta, Masahiro Ichitani
-
Publication number: 20040126932Abstract: A method of manufacturing a semiconductor device is provided including preparing a lead frame having a plurality of leads, wherein the lead widths of the lead tips are smaller than the lead thickness of the tips. A plate is also prepared having a first portion and second portion on a main surface thereof, the second portion being located at the outer periphery of said first portion. A semiconductor chip having a semiconductor element and a plurality of electrodes is fastened to the first portion of the plate and the lead tips are fastened on the second portion of the plate. Bonding wires are then formed to electrically connect the lead tips and the electrodes of the semiconductor chip, and then the lead tips, the plate, the semiconductor chip and the bonding wires are sealed with a molding member.Type: ApplicationFiled: December 15, 2003Publication date: July 1, 2004Inventors: Fujio Ito, Hiroaki Tanaka, Hiromichi Suzuki, Tokuji Toida, Takafumi Konno, Kunihiro Tsubosaki, Shigeki Tanaka, Kazunari Suzuki, Akihiko Kameoka
-
Publication number: 20040005733Abstract: In a method of forming a ball grid array type semiconductor package, a semiconductor chip is mounted through an adhesive material on a surface of a flexible film substrate. Plural bump electrodes are arranged in an array on the opposite side of said substrate and the semiconductor chip is sealed by a resin. In this regard, an insulation layer is formed to cover an electric conductor layer pattern formed on the surface of the substrate, and the semiconductor chip is mounted through an adhesive material on the insulation layer. The insulation layer is divided into a plural number of parts that are mutually discontinuous in the area under the semiconductor chip. By this divided insulation layer, a short circuit between the semiconductor chip and the electric conductor layer pattern is prevented and a deformation of the substrate that comprises the flexible films is suppressed.Type: ApplicationFiled: July 3, 2003Publication date: January 8, 2004Inventors: Atsushi Fujisawa, Takafumi Konno, Shingo Ohsaka, Ryo Haruta, Masahiro Ichitani
-
Patent number: 6673655Abstract: In a semiconductor device having a heat radiation plate, the tips of inner leads connected to a semiconductor chip have a lead width w and a lead thickness t, the width being less than the thickness. The inner leads are secured to the heat radiation plate. Fastening the inner leads to the heat radiation plate supports the latter and eliminates the need for suspending leads. A lead pitch p, the lead width w and lead thickness t of the inner lead tips connected to the semiconductor chip have the relations of w<t and p≦1.2t, with the inner leads secured to the heat radiation plate. The heat radiation plate has slits made therein to form radially shaped heat propagation paths between a semiconductor chip mounting area and the inner leads.Type: GrantFiled: May 23, 2002Date of Patent: January 6, 2004Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd., Hitachi Hokkai Semiconductor, Ltd.Inventors: Fujio Ito, Hiroaki Tanaka, Hiromichi Suzuki, Tokuji Toida, Takafumi Konno, Kunihiro Tsubosaki, Shigeki Tanaka, Kazunari Suzuki, Akihiko Kameoka
-
Patent number: 6590275Abstract: In a ball grid array type semiconductor package, a semiconductor chip is mounted through an adhesive material on a surface of a flexible film substrate. Plural bump electrodes are arranged in an array on the opposite side of said substrate and the semiconductor chip is sealed by a resin. In this regard, an insulation layer is formed to cover an electric conductor layer pattern formed on the surface of the substrate, and the semiconductor chip is mounted through an adhesive material on the insulation layer. The insulation layer is divided into a plural number of parts that are mutually discontinuous in the area under the semiconductor chip. By this divided insulation layer, a short circuit between the semiconductor chip and the electric conductor layer pattern is prevented and a deformation of the substrate that comprises the flexible films is suppressed.Type: GrantFiled: January 31, 2002Date of Patent: July 8, 2003Assignees: Hitachi, Ltd., Hitachi Hokkai Semiconductor, Ltd.Inventors: Atsushi Fujisawa, Takafumi Konno, Shingo Ohsaka, Ryo Haruta, Masahiro Ichitani
-
Patent number: 6551862Abstract: A semiconductor device is disclosed, comprising a tape substrate which supports a semiconductor chip, an insulating adhesive layer disposed between the semiconductor chip and the tape substrate, an insulating sheet member laminated to the insulating adhesive layer and formed harder than the insulating adhesive layer, wires for connecting pads on the semiconductor chip with connecting terminals on the tape substrate, a sealing portion formed by sealing the semiconductor chip with resin, and plural solder balls provided on a back of the tape substrate. A die bonding layer for fixing the semiconductor chip thereto is composed of an insulating adhesive layer and the insulating sheet member laminated thereto. The die bonding layer is formed thick by such a multi-layer structure, whereby the resin balance of the surface and back of the semiconductor chip is improved to prevent warping of a package and improve the mounting temperature cyclicity and reflow characteristic.Type: GrantFiled: October 18, 2001Date of Patent: April 22, 2003Assignees: Hitachi, Ltd., Hitachi Hokkai Semiconductor, Ltd.Inventors: Riyouichi Oota, Tsugihiko Hirano, Atsushi Fujisawa, Takafumi Konno