Abstract: A storage system in which a controller has an encryption-related function is provided. There is provided a storage system including an interface section coupled to one or more storages and a controller that carries out reading and writing processes on the storages via the interface section. The controller includes an arithmetic processing section, a memory, and an encryption processing section. The arithmetic processing section causes the memory to hold data before processing and data after processing by the encryption processing section, and limits the access destination from the storages to the memory. The configuration and actions described above allow the storage system to avoid occurrence of deadlock and the controller to have an encryption-related function.

Abstract: A current sensor for detecting a magnitude of a current flowing through a measuring object has a magnetic core having a first magnetic core and a second magnetic core that is arranged magnetically in parallel to the first magnetic core, wherein the first magnetic core has a magnetic permeability that is higher than that of the second magnetic core in a first frequency band, and the first magnetic core has a magnetic permeability that is lower than that of the second magnetic core in a second frequency band, the second frequency band being higher than the first frequency band, and the current sensor detects the magnitude of the current in a frequency band that is constituted by combining the first frequency band and the second frequency band.

Abstract: A storage apparatus comprises: a plurality of storage devices that read and write data by operating in any one of a plurality of operation modes which vary in electric power consumption; and a control unit that controls the storage devices, wherein each of the plurality of storage devices retains power state information indicating electric power consumption of each of the operation modes; and wherein the control unit acquires the power state information from each of the plurality of storage devices and sets the operation modes for the plurality of storage devices on the basis of the acquired power state information and permissible electric power consumption which can be assigned to each of the storage devices.

Abstract: A current sensor for detecting a magnitude of a current flowing through a measuring object has a magnetic core having a first magnetic core and a second magnetic core that is arranged magnetically in parallel to the first magnetic core, wherein the first magnetic core has a magnetic permeability that is higher than that of the second magnetic core in a first frequency band, and the first magnetic core has a magnetic permeability that is lower than that of the second magnetic core in a second frequency band, the second frequency band being higher than the first frequency band, and the current sensor detects the magnitude of the current in a frequency band that is constituted by combining the first frequency band and the second frequency band.

Abstract: In a breather structure of a transmission, a gear chamber of the transmission is disposed between an engine and an electric motor control device for an electric motor, and a breather piping is inserted into a breather hole in an upper wall of the gear chamber. When viewed from above, in a vehicle width direction, a part of an intake system member and the electric power control device are overlapped together, and a part of the intake system member and the gear chamber are overlapped together. Therefore, a direction of water splashed up from a road surface and flowing forward is changed downward so that the breather hole is easily covered with water. However, since an atmosphere opening part of the breather piping is disposed above the electric motor chamber, even if the breather hole is covered with water, a breather function is not lost.

Abstract: Provided is a multi-node storage system including a plurality of nodes providing a volume to a computer as a logical storage area, each node including a controller that processes an I/O request from the computer, and including a plurality of NVMe drives PCI-connected to any one of the controllers of the node and a switch that connects the controllers of the plurality of nodes to each other, in which the controller includes a plurality of processors that process the I/O request from the computer and a memory, and the memory includes, for the plurality of NVMe drives, virtual queues which are equal in number to processors of a plurality of controllers constituting the multi-node storage system and real queues that store a command in any one of the plurality of NVMe drives and that are smaller in number than the virtual queues.

Abstract: In a breather structure of a transmission, a gear chamber of the transmission is disposed between an engine and an electric motor control device for an electric motor, and a breather piping is inserted into a breather hole in an upper wall of the gear chamber. When viewed from above, in a vehicle width direction, a part of an intake system member and the electric power control device are overlapped together, and a part of the intake system member and the gear chamber are overlapped together. Therefore, a direction of water splashed up from a road surface and flowing forward is changed downward so that the breather hole is easily covered with water. However, since an atmosphere opening part of the breather piping is disposed above the electric motor chamber, even if the breather hole is covered with water, a breather function is not lost.

Abstract: Provided is a multi-node storage system including a plurality of nodes providing a volume to a computer as a logical storage area, each node including a controller that processes an I/O request from the computer, and including a plurality of NVMe drives PCI-connected to any one of the controllers of the node and a switch that connects the controllers of the plurality of nodes to each other, in which the controller includes a plurality of processors that process the I/O request from the computer and a memory, and the memory includes, for the plurality of NVMe drives, virtual queues which are equal in number to processors of a plurality of controllers constituting the multi-node storage system and real queues that store a command in any one of the plurality of NVMe drives and that are smaller in number than the virtual queues.

Abstract: A nonvolatile semiconductor storage apparatus is provided. To a data node and a reference node, a first transistor and a second transistor are respectively connected. In a data state determining operation, in the case where voltage is applied to the data node and reference node, the first and second transistors operate as precharge transistors in a first operation mode, and operate as mirror transistors in a second operation mode. The first and second operation modes are switched.

Abstract: An input/output apparatus according to the present invention has an indication unit and an execution unit. The indication unit indicates that each of a plurality of data blocks between a main memory and a buffer memory is to be transferred. The execution unit transfers one data block relating to a transfer indication sent from the indication unit. After the completion of the transfer, in order to send completion information relating to the one data block to the indication unit, the execution unit determines whether transfers of all of the plurality of data blocks are completed or not based on management information for managing progresses of the transfers of the plurality of data blocks. Once determining that all of the transfers are completed, the execution unit sends, to the indication unit, total completion information showing that all of the transfers are completed.

Abstract: An input/output apparatus according to the present invention has an indication unit and an execution unit. The indication unit indicates that each of a plurality of data blocks between a main memory and a buffer memory is to be transferred. The execution unit transfers one data block relating to a transfer indication sent from the indication unit. After the completion of the transfer, in order to send completion information relating to the one data block to the indication unit, the execution unit determines whether transfers of all of the plurality of data blocks are completed or not based on management information for managing progresses of the transfers of the plurality of data blocks. Once determining that all of the transfers are completed, the execution unit sends, to the indication unit, total completion information showing that all of the transfers are completed.

Abstract: A nonvolatile semiconductor storage apparatus is provided. To a data node and a reference node, a first transistor and a second transistor are respectively connected. In a data state determining operation, in the case where voltage is applied to the data node and reference node, the first and second transistors operate as precharge transistors in a first operation mode, and operate as mirror transistors in a second operation mode. The first and second operation modes are switched.

Abstract: A support structure for a vehicle is interposed between a vehicle body and a vehicle part and is connected with fastening members to support the vehicle part. The support structure is made of a non-ferrous light alloy. Among connecting surfaces of the support structure to which the vehicle body and the vehicle part are connected, an electrochemical corrosion inhibitor is applied to a connecting surface that is located on a lower side, in a vertical direction of the vehicle, of one of the vehicle body and the vehicle part. The one of the vehicle body and the vehicle part corresponds to the applied connecting surface.

Abstract: An HBA driver manages a queue number for enqueuing and dequeuing data to an I/O queue by the main storage, and HBA-F/W manages a storage region at inside of HBA. The HBA driver reduces the number of access times by way of the PCIe bus by noticing an enqueued queue number or a dequeued queue number of an I/O queue to HBA-F/W by utilizing an MMIO area of the main storage in which a storage region on HBA is mapped.

Abstract: A vehicle control device includes a diesel engine, a motor configured to drive a vehicle, a generator configured to generate alternating-current power with an output of the diesel engine, a power storage device configured to charge and discharge direct-current power, a converter configured to convert the alternating-current power generated by the generator into direct-current power and output the direct-current power, and an inverter configured to convert the direct-current power discharged by the power storage device or the direct-current power output by the converter to drive the motor. The converter operates as an inverter during a breakdown of the inverter and drives the motor.

Abstract: A power conversion device includes a converter-inverter controller for controlling a converter and an inverter. The power conversion device further includes a DC capacitor connected between the converter and the inverter and a DC capacitor voltage detector for detecting a DC capacitor voltage Efc between the connection ends of the DC capacitor. The converter-inverter controller provides variable control on the DC capacitor voltage Efc to the converter on the basis of the motor frequency of an AC motor, the DC capacitor voltage Efc, and a pulse mode. Within a predetermined range of motor frequencies, the converter-inverter controller fixes the PWM modulation factor of the inverter to a value m0 and provides operation control to the inverter, where the value m0 being to reduce a harmonic of a predetermined order included in the output voltage from the inverter.

Abstract: In a semiconductor memory device, the output of a regulator is coupled to the inputs of first and second switches, the output of the first switch is coupled to a path for supplying the drain voltage of a memory cell in the first mode, and the output of the second switch is coupled to a path for supplying the gate voltage of the memory cell in the second mode. A fourth switch is placed in parallel with the second switch: the output of the fourth switch is coupled to the output of the second switch, to supply the gate voltage of the memory cell in the first mode. Thus, one regulator is used as both the regulator for the drain voltage of the memory cell and the regulator for the gate voltage of the memory cell.

Abstract: An HBA driver manages a queue number for enqueuing and dequeuing data to an I/O queue by the main storage, and HBA-F/W manages a storage region at inside of HBA. The HBA driver reduces the number of access times by way of the PCIe bus by noticing an enqueued queue number or a dequeued queue number of an I/O queue to HBA-F/W by utilizing an MMIO area of the main storage in which a storage region on HBA is mapped.

Abstract: A vehicle control device includes a diesel engine, a motor configured to drive a vehicle, a generator configured to generate alternating-current power with an output of the diesel engine, a power storage device configured to charge and discharge direct-current power, a converter configured to convert the alternating-current power generated by the generator into direct-current power and output the direct-current power, and an inverter configured to convert the direct-current power discharged by the power storage device or the direct-current power output by the converter to drive the motor. The converter operates as an inverter during a breakdown of the inverter and drives the motor.

Abstract: In a semiconductor memory device, the output of a regulator is coupled to the inputs of first and second switches, the output of the first switch is coupled to a path for supplying the drain voltage of a memory cell in the first mode, and the output of the second switch is coupled to a path for supplying the gate voltage of the memory cell in the second mode. A fourth switch is placed in parallel with the second switch: the output of the fourth switch is coupled to the output of the second switch, to supply the gate voltage of the memory cell in the first mode. Thus, one regulator is used as both the regulator for the drain voltage of the memory cell and the regulator for the gate voltage of the memory cell.