Patents by Inventor Takafumi Mizoguchi
Takafumi Mizoguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9917197Abstract: An object is to provide a method for manufacturing a semiconductor device without exposing a specific layer to moisture or the like at all. A thin film element is manufactured in such a manner that a first film, a second film, and a third film are stacked in this order; a resist mask is formed over the third film; a mask layer is formed by etching the third film with the use of the resist mask; the resist mask is removed; a second layer and a first layer are formed by performing dry etching on the second film and the first film with the use of the mask layer; a fourth film is formed to cover at least the second layer and the first layer; and sidewall layers are formed to cover at least the entire side surfaces of the first layer by performing etch back on the fourth film.Type: GrantFiled: July 26, 2016Date of Patent: March 13, 2018Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Takafumi Mizoguchi, Kojiro Shiraishi, Masashi Tsubuku
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Publication number: 20160336459Abstract: An object is to provide a method for manufacturing a semiconductor device without exposing a specific layer to moisture or the like at all. A thin film element is manufactured in such a manner that a first film, a second film, and a third film are stacked in this order; a resist mask is formed over the third film; a mask layer is formed by etching the third film with the use of the resist mask; the resist mask is removed; a second layer and a first layer are formed by performing dry etching on the second film and the first film with the use of the mask layer; a fourth film is formed to cover at least the second layer and the first layer; and sidewall layers are formed to cover at least the entire side surfaces of the first layer by performing etch back on the fourth film.Type: ApplicationFiled: July 26, 2016Publication date: November 17, 2016Inventors: Takafumi MIZOGUCHI, Kojiro SHIRAISHI, Masashi TSUBUKU
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Patent number: 9437743Abstract: An object is to provide a method for manufacturing a semiconductor device without exposing a specific layer to moisture or the like at all. A thin film element is manufactured in such a manner that a first film, a second film, and a third film are stacked in this order; a resist mask is formed over the third film; a mask layer is formed by etching the third film with the use of the resist mask; the resist mask is removed; a second layer and a first layer are formed by performing dry etching on the second film and the first film with the use of the mask layer; a fourth film is formed to cover at least the second layer and the first layer; and sidewall layers are formed to cover at least the entire side surfaces of the first layer by performing etch back on the fourth film.Type: GrantFiled: September 20, 2011Date of Patent: September 6, 2016Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Takafumi Mizoguchi, Kojiro Shiraishi, Masashi Tsubuku
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Patent number: 9293595Abstract: A manufacturing method of a semiconductor device having a stacked structure in which a lower layer is exposed is provided without increasing the number of masks. A source electrode layer and a drain electrode layer are formed by forming a conductive film to have a two-layer structure, forming an etching mask thereover, etching the conductive film using the etching mask, and performing side-etching on an upper layer of the conductive film in a state where the etching mask is left so that part of a lower layer is exposed. The thus formed source and drain electrode layers and a pixel electrode layer are connected in a portion of the exposed lower layer. In the conductive film, the lower layer and the upper layer may be a Ti layer and an Al layer, respectively. The plurality of openings may be provided in the etching mask.Type: GrantFiled: January 28, 2015Date of Patent: March 22, 2016Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hidekazu Miyairi, Takafumi Mizoguchi
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Patent number: 9276124Abstract: Provided is a method for manufacturing a semiconductor device so as not expose a semiconductor layer to moisture and the number of masks is reduced. For example, a first conductive film, a first insulating film, a semiconductor film, a second conductive film, and a mask film are formed. The first mask film is processed to form a first mask layer. Dry etching is performed on the first insulating film, the semiconductor film, and the second conductive film with the use of the first mask layer to form a thin film stack body, so that a surface of the first conductive film is at least exposed. Sidewall insulating layers covering side surfaces of the thin film stack body are formed. The first conductive film is side-etched to form a first electrode. A second electrode layer is formed with the second mask layer.Type: GrantFiled: January 30, 2014Date of Patent: March 1, 2016Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Takafumi Mizoguchi, Kojiro Shiraishi
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Patent number: 9136286Abstract: It is an object to provide a display panel and an electronic book which are manufactured with high yield and have high reliability. A display panel is provided which includes, a flexible display portion in which a scan line and a signal line intersect with each other over a substrate, a signal line driver circuit for outputting a first signal to the signal line adjacent to a first side of the flexible display portion over the substrate, and a scan line driver circuit for outputting a second signal to the scan line adjacent to a second side of the flexible display portion. In the display panel, the mechanical strength of a portion provided with the signal line driver circuit or the scan line driver circuit is improved as compared to the mechanical strength of other than the portion.Type: GrantFiled: August 4, 2010Date of Patent: September 15, 2015Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Satohiro Okamoto, Takafumi Mizoguchi
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Publication number: 20150144949Abstract: A manufacturing method of a semiconductor device having a stacked structure in which a lower layer is exposed is provided without increasing the number of masks. A source electrode layer and a drain electrode layer are formed by forming a conductive film to have a two-layer structure, forming an etching mask thereover, etching the conductive film using the etching mask, and performing side-etching on an upper layer of the conductive film in a state where the etching mask is left so that part of a lower layer is exposed. The thus formed source and drain electrode layers and a pixel electrode layer are connected in a portion of the exposed lower layer. In the conductive film, the lower layer and the upper layer may be a Ti layer and an Al layer, respectively. The plurality of openings may be provided in the etching mask.Type: ApplicationFiled: January 28, 2015Publication date: May 28, 2015Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hidekazu MIYAIRI, Takafumi MIZOGUCHI
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Patent number: 8946011Abstract: A manufacturing method of a semiconductor device having a stacked structure in which a lower layer is exposed is provided without increasing the number of masks. A source electrode layer and a drain electrode layer are formed by forming a conductive film to have a two-layer structure, forming an etching mask thereover, etching the conductive film using the etching mask, and performing side-etching on an upper layer of the conductive film in a state where the etching mask is left so that part of a lower layer is exposed. The thus formed source and drain electrode layers and a pixel electrode layer are connected in a portion of the exposed lower layer. In the conductive film, the lower layer and the upper layer may be a Ti layer and an Al layer, respectively. The plurality of openings may be provided in the etching mask.Type: GrantFiled: September 1, 2011Date of Patent: February 3, 2015Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hidekazu Miyairi, Takafumi Mizoguchi
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Patent number: 8901561Abstract: A first conductive film, a first insulating film, a semiconductor film, an impurity semiconductor film, a second conductive film, and a first resist mask are formed; first etching is performed to expose at least a surface of the first conductive film; second etching accompanied by side etching is performed on part of the first conductive film to form a gate electrode layer; a second resist mask is formed; third etching is performed to form a source and drain electrode layers, a source and drain regions, and a semiconductor layer; a second insulating film is formed; an opening portion is formed in the second insulating film to partially expose the source or drain electrode layer; a pixel electrode is selectively formed in the opening portion and over the second insulating film; and a supporting portion formed using the gate electrode layer is formed in a region overlapping with the opening portion.Type: GrantFiled: September 21, 2011Date of Patent: December 2, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Takafumi Mizoguchi, Mayumi Mikami, Yumiko Saito
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Patent number: 8741677Abstract: A display device free of contact resistance between a drain electrode (or a source electrode) and a pixel electrode. The display device includes a gate electrode, a gate insulating layer covering the gate electrode, a semiconductor layer formed over the gate insulating layer, and a source electrode and a drain electrode separated from each other and in partial-contact with and over the semiconductor layer, and one of the source electrode and the drain electrode also serves as a pixel electrode, the other of the source electrode and the drain electrode also serves as a signal line, and a low resistant conductive layer is preferably formed over the other of the source electrode and the drain electrode. The low resistant conductive layer can be formed by an electroplating method or the like.Type: GrantFiled: November 29, 2011Date of Patent: June 3, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Takafumi Mizoguchi
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Publication number: 20140147968Abstract: Provided is a method for manufacturing a semiconductor device so as not expose a semiconductor layer to moisture and the number of masks is reduced. For example, a first conductive film, a first insulating film, a semiconductor film, a second conductive film, and a mask film are formed. The first mask film is processed to form a first mask layer. Dry etching is performed on the first insulating film, the semiconductor film, and the second conductive film with the use of the first mask layer to form a thin film stack body, so that a surface of the first conductive film is at least exposed. Sidewall insulating layers covering side surfaces of the thin film stack body are formed. The first conductive film is side-etched to form a first electrode. A second electrode layer is formed with the second mask layer.Type: ApplicationFiled: January 30, 2014Publication date: May 29, 2014Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Takafumi MIZOGUCHI, Kojiro SHIRAISHI
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Patent number: 8735231Abstract: A dual-gate transistor including: a first insulating layer provided to cover a first conductive layer; a first semiconductor layer over the first insulating layer; second semiconductor layers over the first semiconductor layer, the second semiconductor layers are spaced from each other to expose the first semiconductor layer; impurity semiconductor layers over the second semiconductor layers; second conductive layers over the impurity semiconductor layers; second insulating layers over the second conductive layers; a third insulating layer to cover the first semiconductor layer, the second semiconductor layers, the impurity semiconductor layers, the second conductive layers, and the second insulating layers; and a third conductive layer at least over the third insulating layer, and in the dual-gate transistor including the first to third insulating layers with openings, the first insulating layer is substantially equal in thickness to the second insulating layer.Type: GrantFiled: August 22, 2011Date of Patent: May 27, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hidekazu Miyairi, Takafumi Mizoguchi
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Patent number: 8709836Abstract: An object is to provide a method for manufacturing a thin film transistor and a display device with reduced number of masks, in which adverse effects of optical current are suppressed. A manufacturing method comprises forming a stack including, from bottom to top, a light-blocking film, a base film, a first conductive film, a first insulating film, a semiconductor film, an impurity semiconductor film, and a second conductive film; performing first etching on the whole thickness of the stack using a first resist mask formed over it; forming a gate electrode layer by side etching the first conductive film in a second etching; forming a second resist mask over the stack; and performing third etching down to the semiconductor film, and partially etching it, using the second resist mask to form a source and drain electrode layer, a source and drain region, and a semiconductor layer.Type: GrantFiled: July 5, 2011Date of Patent: April 29, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hidekazu Miyairi, Takafumi Mizoguchi
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Patent number: 8679986Abstract: Provided is a method for manufacturing a semiconductor device so as not expose a semiconductor layer to moisture and the number of masks is reduced. For example, a first conductive film, a first insulating film, a semiconductor film, a second conductive film, and a mask film are formed. The first mask film is processed to form a first mask layer. Dry etching is performed on the first insulating film, the semiconductor film, and the second conductive film with the use of the first mask layer to form a thin film stack body, so that a surface of the first conductive film is at least exposed. Sidewall insulating layers covering side surfaces of the thin film stack body are formed. The first conductive film is side-etched to form a first electrode. A second electrode layer is formed with the second mask layer.Type: GrantFiled: September 24, 2011Date of Patent: March 25, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Takafumi Mizoguchi, Kojiro Shiraishi
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Patent number: 8658313Abstract: The characteristics of a power storage device are improved and the lifetime of the power storage device is prolonged. An electrode is manufactured through the following steps: a step of forming an electrode film; a step of forming a damage layer by ion doping on the electrode film; and a step of providing a damage region between the damage layer and a surface. Alkali ion insertion and extraction can be performed by dipping of an electrode, in which the damage layer and the damage region are formed, in a solution containing an alkali ion. A space in which the volume of the electrode is expanded can be secured by the formation of the damage layer and the damage region. Note that another lithium may be used instead of an alkali metal.Type: GrantFiled: September 27, 2010Date of Patent: February 25, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Kazutaka Kuriki, Junpei Momo, Takafumi Mizoguchi
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Patent number: 8546810Abstract: A thin film transistor in which an effect of photo current is small and an On/Off ratio is high is provided. In a bottom-gate bottom-contact (coplanar) thin film transistor, a channel formation region overlaps with a gate electrode, a first impurity semiconductor layer is provided between the channel formation region and a second impurity semiconductor layer which is in contact with a wiring layer. A semiconductor layer which serves as the channel formation region and the first impurity semiconductor layer preferably overlap with each other in a region where they overlap with the gate electrode. The first impurity semiconductor layer and the second impurity semiconductor layer preferably overlap with each other in a region where they do not overlap with the gate electrode.Type: GrantFiled: May 27, 2010Date of Patent: October 1, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hidekazu Miyairi, Yasuhiro Jinbo, Hiromichi Godo, Takafumi Mizoguchi, Shinobu Furukawa
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Patent number: 8427306Abstract: The present invention is an article management system using a central management device with an interrogator and an alarm portion. Because the central management device and a central response device worn by a user of the system are provided separately, loss of the central management device can be prevented. The central response device is worn by a user. The central response device communicates with the central management device wirelessly and includes a detector that detects when the communication distance reaches or exceeds a given value and an alarm portion that notifies the user of this. The central management device communicates wirelessly with one or more articles in which a response device is installed.Type: GrantFiled: November 13, 2007Date of Patent: April 23, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Takafumi Mizoguchi, Hidetomo Kobayashi
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Patent number: 8426945Abstract: To provide a semiconductor device in which a channel formation region can be thinned without adversely affecting a source region and a drain region through a simple process and a method for manufacturing the semiconductor device. In the method for manufacturing a semiconductor device, a semiconductor film, having a thickness smaller than a height of a projection of a substrate, is formed over a surface of the substrate having the projections; the semiconductor film is etched to have an island shape with a resist used as a mask; the resist is etched to expose a portion of the semiconductor film which covers a top surface of the projection; and the exposed portion of the semiconductor film is etched to be thin, while the adjacent portions of the semiconductor film on both sides of the projection remain covered with the resist.Type: GrantFiled: September 6, 2011Date of Patent: April 23, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Masaharu Nagai, Takafumi Mizoguchi
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Patent number: 8299467Abstract: A thin film transistor is provided with a high crystallized region in a channel formation region and a high resistance region between a source and a drain, and thus has a high electric effect mobility and a large on current. The thin film transistor includes an “impurity which suppresses generation of crystal nuclei” contained in the base layer or located on its surface, a first wiring layer over a base layer, an impurity semiconductor layer over the first wiring, a semiconductor layer over the impurity semiconductor layer, the semiconductor layer comprises a crystalline region and a region containing an amorphous phase which is formed adjacent to the base layer.Type: GrantFiled: December 23, 2010Date of Patent: October 30, 2012Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hidekazu Miyairi, Ryu Komatsu, Takafumi Mizoguchi
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Patent number: 8207026Abstract: To provide a method for manufacturing a thin film transistor and a display device using a small number of masks, a thin film transistor is manufactured in such a manner that a first conductive film, an insulating film, a semiconductor film, an impurity semiconductor film, and a second conductive film are stacked; then, a resist mask is formed thereover; first etching is performed to form a thin-film stack body; second etching in which the first conductive film is side-etched is performed by dry-etching to form a gate electrode layer; and a source electrode, a drain electrode, and the like are formed. Before the dry etching, it is preferred that at least a side surface of the etched semiconductor film be oxidized.Type: GrantFiled: January 25, 2010Date of Patent: June 26, 2012Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hideomi Suzawa, Takafumi Mizoguchi, Koji Dairiki, Mayumi Mikami, Yumiko Saito