Patents by Inventor Takaharu Itani
Takaharu Itani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140202387Abstract: A diffusion furnace includes a boat which supports a semiconductor wafer thereon and is rotatable together with the semiconductor wafer. A heater is arranged on the periphery of a core tube which houses the boat therein. The core tube includes a reaction gas supply pipe through which a reaction gas containing a dopant is supplied; and a cooling gas supply pipe through which a cooling gas is supplied toward an outer peripheral portion of the semiconductor wafer.Type: ApplicationFiled: September 3, 2013Publication date: July 24, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yoshifumi NISHIO, Takashi NAKAO, Takaharu ITANI, Akihiro TAKAMI
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Patent number: 8211785Abstract: A shallow p-n junction diffusion layer having a high activation rate of implanted ions, low resistivity, and a controlled leakage current is formed through annealing. Annealing after impurities have been doped is carried out through light irradiation. Those impurities are activated by annealing at least twice through light irradiation after doping impurities to a semiconductor substrate 11. The light radiations are characterized by usage of a W halogen lamp RTA or a flash lamp FLA except for the final light irradiation using a flash lamp FLA. Impurity diffusion may be controlled to a minimum, and crystal defects, which have developed in an impurity doping process, may be sufficiently reduced when forming ion implanted layers in a source and a drain extension region of the MOSFET or ion implanted layers in a source and a drain region.Type: GrantFiled: June 29, 2007Date of Patent: July 3, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Takaharu Itani, Takayuki Ito, Kyoichi Suguro
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Patent number: 8211796Abstract: A semiconductor device manufacturing method has conducting first heating processing at a first heating temperature in an inert atmosphere under a first pressure in a first process chamber to silicide an upper part of the source-drain diffusion layer and form a silicide film; conducting second heating processing at a second heating temperature in an oxidizing atmosphere under a second pressure in a second process chamber to selectively oxidize at least a surface of the metal film on the element isolating insulation film and form a metal oxide film; conducting third heating processing at a third heating temperature which is higher than the first heating temperature and the second heating temperature in an atmosphere in a third process chamber to increase a concentration of silicon in the silicide film; and selectively removing the metal oxide film and an unreacted part of the metal film on the element isolating insulation film.Type: GrantFiled: October 27, 2011Date of Patent: July 3, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Takaharu Itani, Koji Matsuo, Kazuhiko Nakamura
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Patent number: 8148717Abstract: A manufacturing method for semiconductor device includes: forming an opening, in a surface of a semiconductor substrate being composed of first atom, the opening having an opening ratio y to an area of the surface of the semiconductor substrate ranging from 5 to 30%; forming an epitaxial layer in the opening, the epitaxial layer being made of a mixed crystal containing a second atom in a concentration ranging from 15 to 25%, and the second atom having a lattice constant different from a lattice constant of the first atom; implanting impurity ion into the epitaxial layer; and performing activation annealing at a predetermined temperature T, the predetermined temperature T being equal to or higher than 1150° C. and satisfies a relationship of y?1E-5exp (21541/T).Type: GrantFiled: January 28, 2011Date of Patent: April 3, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Takayuki Ito, Yusuke Oshiki, Kouji Matsuo, Kenichi Yoshino, Takaharu Itani, Takuo Ohashi, Toshihiko Iinuma, Kiyotaka Miyano, Kunihiro Miyazaki
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Publication number: 20120040526Abstract: A semiconductor device manufacturing method has conducting first heating processing at a first heating temperature in an inert atmosphere under a first pressure in a first process chamber to silicide an upper part of the source-drain diffusion layer and form a silicide film; conducting second heating processing at a second heating temperature in an oxidizing atmosphere under a second pressure in a second process chamber to selectively oxidize at least a surface of the metal film on the element isolating insulation film and form a metal oxide film; conducting third heating processing at a third heating temperature which is higher than the first heating temperature and the second heating temperature in an atmosphere in a third process chamber to increase a concentration of silicon in the silicide film; and selectively removing the metal oxide film and an unreacted part of the metal film on the element isolating insulation film.Type: ApplicationFiled: October 27, 2011Publication date: February 16, 2012Applicant: Kabushiki Kaisha ToshibaInventors: Takaharu Itani, Koji Matsuo, Kazuhiko Nakamura
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Patent number: 8101974Abstract: A semiconductor device subjected to an optical annealing process by radiation light whose principal wavelength is 1.5 ?m or less includes a circuit pattern region formed on a semiconductor substrate, and a dummy pattern region formed separately from the circuit pattern region on the semiconductor substrate. The circuit pattern region has an integrated circuit pattern containing a gate pattern related to a circuit operation. The dummy pattern region has dummy gate patterns that have the same structure as that of a gate pattern used in the integrated circuit pattern and the dummy gate patterns are repeatedly arranged with a pitch 0.4 times or less the principal wavelength.Type: GrantFiled: December 4, 2008Date of Patent: January 24, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Ohno, Takaharu Itani, Eiji Morifuji, Norikazu Ooishi, Toshihiko Iinuma, Yoshinori Honguh
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Patent number: 8062973Abstract: A semiconductor device manufacturing method has conducting first heating processing at a first heating temperature in an inert atmosphere under a first pressure in a first process chamber to silicide an upper part of the source-drain diffusion layer and form a silicide film; conducting second heating processing at a second heating temperature in an oxidizing atmosphere under a second pressure in a second process chamber to selectively oxidize at least a surface of the metal film on the element isolating insulation film and form a metal oxide film; conducting third heating processing at a third heating temperature which is higher than the first heating temperature and the second heating temperature in an atmosphere in a third process chamber to increase a concentration of silicon in the silicide film; and selectively removing the metal oxide film and an unreacted part of the metal film on the element isolating insulation film.Type: GrantFiled: January 25, 2010Date of Patent: November 22, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Takaharu Itani, Koji Matsuo, Kazuhiko Nakamura
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Publication number: 20110127578Abstract: A manufacturing method for semiconductor device includes: forming an opening, in a surface of a semiconductor substrate being composed of first atom, the opening having an opening ratio y to an area of the surface of the semiconductor substrate ranging from 5 to 30%; forming an epitaxial layer in the opening, the epitaxial layer being made of a mixed crystal containing a second atom in a concentration ranging from 15 to 25%, and the second atom having a lattice constant different from a lattice constant of the first atom; implanting impurity ion into the epitaxial layer; and performing activation annealing at a predetermined temperature T, the predetermined temperature T being equal to or higher than 1150° C. and satisfies a relationship of y?1E-5exp (21541/T).Type: ApplicationFiled: January 28, 2011Publication date: June 2, 2011Applicant: Kabushiki Kaisha ToshibaInventors: Takayuki Ito, Yusuke Oshiki, Kouji Matsuo, Kenichi Yoshino, Takaharu Itani, Takuo Ohashi, Toshihiko Iinuma, Kiyotaka Miyano, Kunihiro Miyazaki
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Patent number: 7902030Abstract: A manufacturing method for semiconductor device includes: forming an opening, in a surface of a semiconductor substrate being composed of first atom, the opening having an opening ratio y to an area of the surface of the semiconductor substrate ranging from 5 to 30%; forming an epitaxial layer in the opening, the epitaxial layer being made of a mixed crystal containing a second atom in a concentration ranging from 15 to 25%, and the second atom having a lattice constant different from a lattice constant of the first atom; implanting impurity ion into the epitaxial layer; and performing activation annealing at a predetermined temperature T, the predetermined temperature T being equal to or higher than 1150° C. and satisfies a relationship of y?1E-5exp(21541/T).Type: GrantFiled: June 12, 2009Date of Patent: March 8, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Takayuki Ito, Yusuke Oshiki, Kouji Matsuo, Kenichi Yoshino, Takaharu Itani, Takuo Ohashi, Toshihiko Iinuma, Kiyotaka Miyano, Kunihiro Miyazaki
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Publication number: 20100190336Abstract: A semiconductor device manufacturing method has conducting first heating processing at a first heating temperature in an inert atmosphere under a first pressure in a first process chamber to silicide an upper part of the source-drain diffusion layer and form a silicide film; conducting second heating processing at a second heating temperature in an oxidizing atmosphere under a second pressure in a second process chamber to selectively oxidize at least a surface of the metal film on the element isolating insulation film and form a metal oxide film; conducting third heating processing at a third heating temperature which is higher than the first heating temperature and the second heating temperature in an atmosphere in a third process chamber to increase a concentration of silicon in the silicide film; and selectively removing the metal oxide film and an unreacted part of the metal film on the element isolating insulation film.Type: ApplicationFiled: January 25, 2010Publication date: July 29, 2010Inventors: Takaharu Itani, Koji Matsuo, Kazuhiko Nakamura
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Patent number: 7643736Abstract: An apparatus for manufacturing a semiconductor device includes a treatment chamber in which a working substrate is disposed; a plurality of lamps provided above the treatment chamber; and a reflector provided behind the lamps relative to a direction towards the working substrate, spatially controlling an in-plane distribution of reflection rate of light beams from the lamps, and irradiating the working substrate with light from the lamps.Type: GrantFiled: March 27, 2007Date of Patent: January 5, 2010Assignee: Kabushiki Kaisha ToshibaInventor: Takaharu Itani
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Publication number: 20090309133Abstract: A manufacturing method for semiconductor device includes: forming an opening, in a surface of a semiconductor substrate being composed of first atom, the opening having an opening ratio y to an area of the surface of the semiconductor substrate ranging from 5 to 30%; forming an epitaxial layer in the opening, the epitaxial layer being made of a mixed crystal containing a second atom in a concentration ranging from 15 to 25%, and the second atom having a lattice constant different from a lattice constant of the first atom; implanting impurity ion into the epitaxial layer; and performing activation annealing at a predetermined temperature T, the predetermined temperature T being equal to or higher than 1150° C. and satisfies a relationship of y?1E-5exp(21541/T).Type: ApplicationFiled: June 12, 2009Publication date: December 17, 2009Inventors: Takayuki Ito, Yusuke Oshiki, Kouji Matsuo, Kenichi Yoshino, Takaharu Itani, Takuo Ohashi, Toshihiko Iinuma, Kiyotaka Miyano, Kunihiro Miyazaki
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Publication number: 20090146310Abstract: A semiconductor device subjected to an optical annealing process by radiation light whose principal wavelength is 1.5 ?m or less includes a circuit pattern region formed on a semiconductor substrate, and a dummy pattern region formed separately from the circuit pattern region on the semiconductor substrate. The circuit pattern region has an integrated circuit pattern containing a gate pattern related to a circuit operation. The dummy pattern region has dummy gate patterns that have the same structure as that of a gate pattern used in the integrated circuit pattern and the dummy gate patterns are repeatedly arranged with a pitch 0.4 times or less the principal wavelength.Type: ApplicationFiled: December 4, 2008Publication date: June 11, 2009Inventors: Hiroshi Ohno, Takaharu Itani, Eiji Morifuji, Norikazu Ooishi, Toshihiko Iinuma, Yoshinori Honguh
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Publication number: 20090137107Abstract: A method of manufacturing a semiconductor device according to an embodiment of the invention includes forming patterns on a substrate, depositing a light absorption layer on the patterns, processing the light absorption layer to form a first region which includes a first type of pattern included in the patterns and is coated with the light absorption layer having a first thickness, a second region which includes a second type of pattern included in the patterns and is coated with the light absorption layer having a second thickness thinner than the first thickness, and a third region which includes a third type of pattern included in the patterns and is coated with the light absorption layer having a third thickness thinner than the second thickness, and annealing the substrate by radiating light on the substrate.Type: ApplicationFiled: November 26, 2008Publication date: May 28, 2009Inventor: Takaharu Itani
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Publication number: 20080268660Abstract: A method of manufacturing a semiconductor device that involves a heat treatment of a semiconductor substrate, has removing a superficial layer from an upper surface of an edge part of said semiconductor substrate, a bevel surface of the edge part of said semiconductor substrate and a side surface of the edge part of said semiconductor substrate; and conducting the heat treatment of said semiconductor substrate by irradiating said semiconductor substrate with light having a pulse width of 0.1 milliseconds to 100 milliseconds from a light source after said superficial layer is removed.Type: ApplicationFiled: April 24, 2008Publication date: October 30, 2008Inventors: Takaharu Itani, Kenichi Yoshino, Takayuki Ito, Takashi Kawakami, Tetsuya Kugimiya
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Publication number: 20080260501Abstract: A shallow p-n junction diffusion layer having a high activation rate of implanted ions, low resistivity, and a controlled leakage current is formed through annealing. Annealing after impurities have been doped is carried out through light irradiation. Those impurities are activated by annealing at least twice through light irradiation after doping impurities to a semiconductor substrate 11. The light radiations are characterized by usage of a W halogen lamp RTA or a flash lamp FLA except for the final light irradiation using a flash lamp FLA. Impurity diffusion may be controlled to a minimum, and crystal defects, which have developed in an impurity doping process, may be sufficiently reduced when forming ion implanted layers in a source and a drain extension region of the MOSFET or ion implanted layers in a source and a drain region.Type: ApplicationFiled: June 29, 2007Publication date: October 23, 2008Applicant: Kabushiki Kaisha ToshibaInventors: Takaharu Itani, Takayuki Ito, Kyoichi Suguro
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Publication number: 20070243701Abstract: An impurity is ion-implanted into the major surface of an Si substrate having a bulk microdefect density of 5×106 to 5×107 cm?3, a bulk microdefect size smaller than 100 nm, and a dissolved oxygen concentration of 1.1×1018 to 1.2×1018 cm?3. The Si substrate then undergoes ultra-rapid thermal annealing whose heating/cooling rate is higher than 1×105° C./sec, thereby electrically activating the impurity to form at least a partial impurity diffusion layer of a semiconductor element.Type: ApplicationFiled: April 5, 2007Publication date: October 18, 2007Inventors: Takayuki Ito, Kyoichi Suguro, Takaharu Itani, Yoshihiko Saito
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Patent number: 7279405Abstract: A shallow p-n junction diffusion layer having a high activation rate of implanted ions, low resistivity, and a controlled leakage current is formed through annealing. Annealing after impurities have been doped is carried out through light irradiation. Those impurities are activated by annealing at least twice through light irradiation after doping impurities to a semiconductor substrate 11. The light radiations are characterized by usage of a W halogen lamp RTA or a flash lamp FLA except for the final light irradiation using a flash lamp FLA. Impurity diffusion maybe controlled to a minimum, and crystal defects, which have developed in an impurity doping process, may be sufficiently reduced when forming ion implanted layers in a source and a drain extension region of the MOSFET or ion implanted layers in a source and a drain region.Type: GrantFiled: November 4, 2004Date of Patent: October 9, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Takaharu Itani, Takayuki Ito, Kyoichi Suguro
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Publication number: 20070232083Abstract: An apparatus for manufacturing a semiconductor device includes a treatment chamber in which a working substrate is disposed; a plurality of lamps provided above the treatment chamber; and a reflector provided behind the lamps relative to a direction towards the working substrate, spatially controlling an in-plane distribution of reflection rate of light beams from the lamps, and irradiating the working substrate with light from the lamps.Type: ApplicationFiled: March 27, 2007Publication date: October 4, 2007Inventor: Takaharu Itani
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Patent number: 7084068Abstract: An annealing furnace, includes a processing chamber configured to store a substrate; a susceptor located in the processing chamber so as to load the substrate and having an auxiliary heater for heating the substrate at 650° C. or less, the susceptor having a surface being made of quartz; a gas supply system configured to supply a gas required for a thermal processing on the substrate in parallel to a surface of the substrate; a transparent window located on an upper part of the processing chamber facing the susceptor; and a main heater configured to irradiate a pulsed light on the surface of the substrate to heat the substrate from the transparent window, the pulsed light having a pulse duration of approximately 0.1 ms to 200 ms and having a plurality of emission wavelengths.Type: GrantFiled: September 15, 2003Date of Patent: August 1, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Kyoichi Suguro, Takayuki Ito, Takaharu Itani