Abstract: A graphics display system includes a host processor calculating graphic data and providing the graphic data to a graphics processor, and frame memories which store the graphic pixel data and supply display data to display devices. The graphics display system also includes a first register group which stores the graphics data, a second register group which converts and/or stores the data in the first register group, a pixel generator which generates pixels according to the graphic data in the second register group, and a plotter which writes the pixel data generated in the pixel generator in the frame memories. The second register group fetches the data from the first register group when the host processor issues a command for plotting, holds the data previously written by the host processor. At the same time, when the host processor issues a command for plotting, the specified graphic type is written in the graphic processor as well as data calculated based on the first and second register groups.

Abstract: A graphics display system includes a host processor calculating graphic data and providing the graphic data to a graphics processor, and frame memories which store the graphic pixel data and supply display data to display devices. The graphics display system also includes a first register group which stores the graphics data, a second register group which converts and/or stores the data in the first register group, a pixel generator which generates pixels according to the graphic data in the second register group, and a plotter which writes the pixel data generated in the pixel generator in the frame memories. The second register group fetches the data from the first register group when the host processor issues a command for plotting, holds the data previously written by the host processor. At the same time, when the host processor issues a command for plotting, the specified graphic type is written in the graphic processor as sell as data calculated based on the first and second register groups.

Abstract: A semiconductor gate array device compatible with ECL and/or TTL, wherein the input buffer unit includes a TTL input stage, an ECL input stage and a common output stage, and the output buffer unit includes a common input stage, an ECL output stage and a TTL output stage. When the device is to be used as a TTL input interface, the TTL input stage and the common output stage are coupled together and when the device is to be used as an ECL input interface, the ECL input stage and the common output stage are coupled together. When used as a TTL output interface, the common input stage and the TTL output stage are coupled together and when used as an ECL output interface, the common input stage and the ECL output stage are coupled together. Therefore, the input/output interfaces exhibit general applicability to meet the user's demands, yet enabling the layout areas of the input and output buffer portions to be decreased.