Abstract: An automatic gain control device includes amplifiers cascaded, each having a variable gain; level measurement portions respectively corresponding to the amplifiers, where each of the level measurement portions measures a level of an output signal of a corresponding one of the amplifiers in a level measurement period indicated by a level measurement signal; error calculators respectively corresponding to the level measurement portions, where each of the error calculators compares a level measured by a corresponding one of the level measurement portions with a threshold which is set so that a corresponding one of the amplifiers will not saturate, and outputs a comparison result as an error signal; a gain computation section which updates one of the gains of the amplifiers at a time corresponding to a gain update signal, based on the error signals; and an operation controller which generates the level measurement signal and the gain update signal.

Abstract: An automatic gain control device includes an amplifier which amplifies an input signal based on a gain control signal, and outputs an amplified signal, a converter which converts the amplified signal into a converted signal having a value corresponding to an absolute value of the amplified signal, a peak detector which removes, during a peak detection period, from values of the converted signal, a predetermined number of values which include a maximum value, and determines a peak level of the converted signal after the removing, an error calculator which calculates an error between the peak level and a reference signal, and outputs the error as an error signal, and a gain controller which updates the gain control signal based on the error signal, and outputs an updated gain control signal.

Abstract: An object is to achieve reduction of a spurious in a delta-sigma type fraction division PLL synthesizer. In its configuration, first and second L-value accumulators 31 and 30 are provided. The difference between overflow signals 16 and 17 of the first and the second L-value accumulators 31 and 30 is acquired by an adder 29, so that in response to an output signal of the adder 29, a division ratio of a variable divider 2 having a division ratio switchable between M, M+1, and M?1 is switched. By virtue of this, the frequency of a spurious generated by operation noise of the first and the second L-value accumulators 31 and 30 is shifted to a frequency component higher than the prior art so that the spurious is removed by a loop filter (low pass filter) 5.

Abstract: The present invention provides a transmitter conforming to the EER method in a wide frequency band at high efficiency. For this purpose, the amplitude component of a modulated signal is input to the power supply terminal of a high-frequency power amplifier 130, the I and Q quadrature signals thereof are input to the high-frequency input terminal of the high-frequency power amplifier 130, and the original modulated signal is obtained from the output of the high-frequency power amplifier 130. A collector voltage is supplied from DC—DC converter group 615 having output voltages being different sequentially to an emitter follower 729 via a switch group 621.

Abstract: The present invention provides a transmitter conforming to the EER method in a wide frequency band at high efficiency. For this purpose, the amplitude component of a modulated signal is input to the power supply terminal of a high-frequency power amplifier 130, the I and Q quadrature signals thereof are input to the high-frequency input terminal of the high-frequency power amplifier 130, and the original modulated signal is obtained from the output of the high-frequency power amplifier 130. A collector voltage is supplied from DC-DC converter group 615 having output voltages being different sequentially to an emitter follower 729 via a switch group 621.

Abstract: A fractional frequency divider (28) includes a latch (31) for holding frequency division data, a ?? modulator (33), a digital dither circuit (32) for receiving a digital input F representing fraction part of the frequency division data from the latch (31) and supplying a digital output alternately changing between F+k and F?k (where k is an integer) or a F value itself to the ?? modulator (33), and circuit means (34 through 38) for executing fractional frequency division based on integer part (M value) of the frequency division data and an output of the ?? modulator (33). The digital dither circuit (32) is useful for suppressing a spurious signal generated as a result of concentration of quantization noise at a particular frequency when the ?? modulator (33) receives a particular F value (e.g., F=2n?1).

Abstract: A fractional frequency divider (28) includes a latch (31) for holding frequency division data, a ?? modulator (33), a digital dither circuit (32) for receiving a digital input F representing fraction part of the frequency division data from the latch (31) and supplying a digital output alternately changing between F+k and F?k (where k is an integer) or a F value itself to the ?? modulator (33), and circuit means (34 through 38) for executing fractional frequency division based on integer part (M value) of the frequency division data and an output of the ?? modulator (33). The digital dither circuit (32) is useful for suppressing a spurious signal generated as a result of concentration of quantization noise at a particular frequency when the ?? modulator (33) receives a particular F value (e.g., F=2n?1).

Abstract: A temperature compensating crystal oscillation device includes a constant voltage circuit (12) for outputting a predetermined voltage independent of the ambient temperature, a temperature sensor circuit (13) for outputting a voltage in proportion to the ambient temperature, and a control circuit (14) for receiving the constant voltage output from the constant voltage circuit (12) and the voltage output in proportion to the temperature from the temperature sensor circuit (13) and for generating a control voltage (Vc) used for compensating a temperature characteristic of a quartz oscillator in the entire range of the ambient temperature through polygonal lines approximation of a negative cubic curve by using continuous lines.

Abstract: In order to realize highly accurate temperature compensation of a crystal oscillation frequency, a current in proportion to the cube of a difference between an ambient temperature T.sub.a and a reference temperature T.sub.0 is generated. For this purpose, provided are a first series circuit of two diodes; a second series circuit of three diodes; a third series circuit of two diodes; a fourth series circuit of three diodes; a current source for allowing a constant current to flow into the first series circuit; a current source for allowing a constant current to flow from the third series circuit; a current source for allowing a current in proportion to T.sub.a -T.sub.0 to flow into the second series circuit when T.sub.a .gtoreq.T.sub.0 and allowing a current in proportion to .vertline.T.sub.a -T.sub.0 .vertline. to flow from the fourth series circuit when T.sub.a <T.sub.