Abstract: A write disturbance margin of reference cells that generate reference current during read is improved. A bit line forms a clad interconnect structure in the normal cell region where normal cells are disposed, and a partially clad or non-clad interconnect structure in the reference cell region where a reference cell is disposed. Thus, a writing magnetic field intensity applied to the reference cell is smaller than the write magnetic field intensity applied to a normal memory cell during identical write currents.

Abstract: A semiconductor device having first and second digit line drivers and a bit line driver. When the address of one segment has been input from the outside, a segment decoder selects one segment corresponding to the address and couples the same to the selected first digit line driver. When the addresses of two or more segments have been input from the outside, the segment decoder selects two or more segments corresponding to the addresses and couples the selected two or more segments to the respective digital line drivers.

Abstract: A semiconductor device using a segment writing method capable of achieving a normal write operation is provided. The first DL driver and the second DL driver each cause a magnetizing current to flow through a digit line of a selected block. A BL driver causes a write current to flow in a direction corresponding to the logic of a data signal to all bit lines in a selected segment, and writes the data signal to a memory cell of the selected block. A segment decoder, when the address of one segment has been input from the outside, selects one segment corresponding to the address and couples the same to the selected first DL driver, and the segment decoder, when the addresses of two or more segments have been input from the outside, selects two or more segments corresponding to the addresses and couples the selected two or more segments to the first DL driver and the second DL driver, respectively.

Abstract: A semiconductor device which it can accommodate variations in a write current threshold in each memory cell and can secure a write margin is provided. An MRAM device includes an MTJ memory cell arranged in a matrix, plural bit lines each arranged corresponding to a memory cell column, plural digit lines each arranged corresponding to a memory cell row, and a write current adjusting unit which adjusts a current amount of a write current to be flowed through a bit line and/or a digit line, in order to perform a data write to each MTJ memory cell normally. The write current adjusting unit divides the plural bit lines and/or the plural digit lines into units of at least one write current line as division units, and includes plural write current adjusting circuits which adjust the current amount of write current in each of the division units.

Abstract: A magnetic memory device is provided in which, even when a recording layer having an asymmetric shape and a local via are formed over a strap wiring with a sufficient distance allowed therebetween, increase in the size of the magnetic memory device can be suppressed. The magnetic memory device includes the strap wiring, the local via, and a magnetic recording element (TMR element). The TMR element includes a fixed layer and the recording layer. The planar shape of the recording layer is asymmetric with respect to the direction of the easy magnetization axis of the recording layer and is symmetric with respect to the axis of symmetry perpendicular to the easy magnetization axis. The contoured portion of the recording layer on the side closer to the center of area of the recording layer is opposed to the local via formation side.

Abstract: A write disturbance margin of reference cells that generate reference current during read is improved. A bit line forms a clad interconnect structure in the normal cell region where normal cells are disposed, and a partially clad or non-clad interconnect structure in the reference cell region where a reference cell is disposed. Thus, a writing magnetic field intensity applied to the reference cell is smaller than the write magnetic field intensity applied to a normal memory cell during identical write currents.

Abstract: The invention provides a semiconductor device having a lower probability of erroneous inversion of data signal. The MRAM disclosed herein comprises (m+1)×(n+1) memory cells arranged in (m+1) rows and (n+1) columns, digit lines respectively provided in the rows, and bit lines respectively provided in the columns. A magnetizing current Im caused to flow through a digit line in a selected row makes all memory cells half-selected in the row, while a writing current is caused to flow through (n+1) bit lines to write data signals of (n+1) bits into the (n+1) memory cells, the direction of the writing current depending on the logic of each of these data signals. Thus, erroneous inversion of data signal due to a magnetic field in a digit line is avoided.

Abstract: A magnetic memory device is provided in which, even when a recording layer having an asymmetric shape and a local via are formed over a strap wiring with a sufficient distance allowed therebetween, increase in the size of the magnetic memory device can be suppressed. The magnetic memory device includes the strap wiring, the local via, and a magnetic recording element (TMR element). The TMR element includes a fixed layer and the recording layer. The planar shape of the recording layer is asymmetric with respect to the direction of the easy magnetization axis of the recording layer and is symmetric with respect to the axis of symmetry perpendicular to the easy magnetization axis. The contoured portion of the recording layer on the side closer to the center of area of the recording layer is opposed to the local via formation side.

Abstract: Magnetic memory devices integrated together with a logic circuit on a common semiconductor chip are arranged to have layouts mirror-symmetrical (mirror inversion) with respect to an axis parallel to a magnetization-hard axis of a magneto-resistance element of a magnetic memory cell in the magnetic memory device. The logic circuit is arranged between the magnetic memory devices. The magnetic memory device capable accurately of maintaining integrity in logical level between write data and read data is achieved.

Abstract: A semiconductor integrated circuit device includes a plurality of memory cells storing data; a write current line arranged near the memory cells or electrically connected to the memory cells; a first constant current generating circuit providing an output current having a temperature dependence; a second constant current generating circuit providing an output current having a temperature dependence different from that of the output current of the first constant current generating circuit; a mixing circuit mixing the output currents of the constant current generating circuits together to provide a composite current at a variable mixing rate; and a write current electrically connected to the write current line and writing data into the memory cell by passing a write circuit through the write current line based on the composite current provided by the mixing circuit.

Abstract: Source lines for a spin injection magnetic memory cell are arranged parallel to word lines for executing writing/reading of data multiple bits at a time. In a write operation, a source line potential changes in a predetermined sequence such that the source line commonly connected to a plurality of selected memory cells is set to pass a current only in one direction in each stage of the operation sequence. For the data write sequence, a current is caused to flow through memory cells according to write data sequentially, or the memory cell has a resistance state set to an initial resistance state before writing, and then changed to a state according to the write data Fast writing can be achieved in the magnetic memory without increasing a memory cell layout area.

Abstract: Magnetic memory devices integrated together with a logic circuit on a common semiconductor chip are arranged to have layouts mirror-symmetrical (mirror inversion) with respect to an axis parallel to a magnetization-hard axis of a magneto-resistance element of a magnetic memory cell in the magnetic memory device. The logic circuit is arranged between the magnetic memory devices. The magnetic memory device capable accurately of maintaining integrity in logical level between write data and read data is achieved.

Abstract: Magnetic memory devices integrated together with a logic circuit on a common semiconductor chip are arranged to have layouts mirror-symmetrical (mirror inversion) with respect to an axis parallel to a magnetization-hard axis of a magneto-resistance element of a magnetic memory cell in the magnetic memory device. The logic circuit is arranged between the magnetic memory devices. The magnetic memory device capable accurately of maintaining integrity in logical level between write data and read data is achieved.

Abstract: Source lines for a spin injection magnetic memory cell are arranged parallel to word lines for executing writing/reading of data multiple bits at a time. In a write operation, a source line potential changes in a predetermined sequence such that the source line commonly connected to a plurality of selected memory cells is set to pass a current only in one direction in each stage of the operation sequence. For the data write sequence, a current is caused to flow through memory cells according to write data sequentially, or the memory cell has a resistance state set to an initial resistance state before writing, and then changed to a state according to the write data Fast writing can be achieved in the magnetic memory without increasing a memory cell layout area.

Abstract: Normal memory cells and dummy cells are arranged continuously in a memory array. In a data read operation, first and second data lines are connected to the selected memory cell and the dummy cell, respectively, and are supplied with operation currents of a differential amplifier. An offset corresponding to a voltage difference between first and second offset control voltages applied from voltage generating circuits are provided between passing currents of the first and second data lines, and a reference current passing through the dummy cell is set to a level intermediate between two kinds of levels corresponding to storage data of a data read current passing through the selected memory cell.

Abstract: A semiconductor integrated circuit device includes a plurality of memory cells storing data; a write current line arranged near the memory cells or electrically connected to the memory cells; a first constant current generating circuit providing an output current having a temperature dependence; a second constant current generating circuit providing an output current having a temperature dependence different from that of the output current of the first constant current generating circuit; a mixing circuit mixing the output currents of the constant current generating circuits together to provide a composite current at a variable mixing rate; and a write current electrically connected to the write current line and writing data into the memory cell by passing a write circuit through the write current line based on the composite current provided by the mixing circuit.

Abstract: A terminating circuit for terminating a common data bus to a predetermined voltage level is inactivated in a test mode, a level detection circuit detects a potential of an internal test data bus line coupled to the common data bus line, and an output state of a ternary output circuit is controlled in accordance with a detection result. In a semiconductor integrated circuit device including the memory integrated together with a logic on a common semiconductor substrate, it is accurately determined whether the output state of the memory is a ternary state while operating the memory under actual operation conditions.

Abstract: Magnetic memory devices integrated together with a logic circuit on a common semiconductor chip are arranged to have layouts mirror-symmetrical (mirror inversion) with respect to an axis parallel to a magnetization-hard axis of a magneto-resistance element of a magnetic memory cell in the magnetic memory device. The logic circuit is arranged between the magnetic memory devices. The magnetic memory device capable accurately of maintaining integrity in logical level between write data and read data is achieved.

Abstract: In a shift switch circuit for replacing a data line, a transmission gate circuit connecting node N2 corresponding to ith write data line to node N4 corresponding to ith read data line is provided. An operation of the shift switch circuit can be confirmed according to whether or not an output corresponding to provided data input signal D<i> is observed as data output signal Q<i>. Preferably, a transmission gate connecting i+1th write data line to an output data line is further provided, in order to further ensure operation confirmation. When a fuse circuit is set to replace a data line, ratio of successful chip repairing will be higher.

Abstract: Each of N memory blocks of first to Nth stages includes a plurality of first and second driver units. The plurality of first and second driver units are respectively provided corresponding to one end and another end of a plurality of digit lines included in each memory block. Each of the first driver units in memory blocks before a selected memory block connects a corresponding digit line to a first voltage according to a voltage level on a digit line of the same row in a memory block of a previous stage. A second driver unit in the selected memory block connects a corresponding digit line to a second voltage in order to supply a data write current. In other words, digit lines in the memory blocks before the selected memory block are not used as current lines but as signal lines.