Patents by Inventor Takaharu Yamada

Takaharu Yamada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240080403
    Abstract: An image processing apparatus includes a processor configured to: extract a first target image corresponding to a reading target having a glossy portion and a non-glossy portion from a first read image acquired by optically reading the reading target in a first reading environment, and extract a second target image corresponding to the reading target from a second read image acquired by optically reading the reading target in a second reading environment in which specular light acquired from the reading target by an image sensor is of higher intensity compared to the first reading environment; execute an alignment of the first target image and the second target image if positions of the first and second target images do not coincide with each other and if the first and second target images are alignable by translating or rotating at least one of the first target image or the second target image; and form a composite image by executing a composition process that composites a non-glossy region corresponding to
    Type: Application
    Filed: March 3, 2023
    Publication date: March 7, 2024
    Applicant: FUJIFILM Business Innovation Corp.
    Inventors: Kenji YAMADA, Takaharu Sato
  • Patent number: 11849249
    Abstract: The present technology relates to a file generation device, a file generation method, a file reproduction device, a file reproduction method, and a program capable of associating an image stored is a file with external data outside the file. A file control unit generates an association-type high efficiency image file format (HEIF) file in which an image in an HEIF file compliant with HEIF and specific information that specifies external data outside the HEIF file, the external data to be associated with the image, are stored in association with each other. Furthermore, the file control unit reproduces the association-type HEIF file. The present technology can be applied to a case where an HEIF file is generated or a case where the HEIF file is reproduced.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: December 19, 2023
    Assignee: Sony Group Corporation
    Inventors: Daisuke Funamoto, Ryogo Ito, Yukio Isobe, Toshihiro Ishizaka, Yuji Matsui, Takaharu Yamada
  • Publication number: 20220309035
    Abstract: The present technology relates to a file processing device, a file processing method, and a program that enable association of, for example, an image stored in a file with external data outside the file. A file control unit generates a high efficiency image file format (HEIF) file storing relationship information related to association between an image and specification information. The relationship information includes the specification information that is before being assigned to external data and specifies the external data that is outside the HEIF file and is to be associated with the image stored in the HEIF file. Furthermore, the file control unit writes the specification information stored in the HEIF file into the file storing the external data. The present technology can be applied to, for example, a case where a HEIF file is generated and an image stored in the HEIF file is associated with external data later, and the like.
    Type: Application
    Filed: June 5, 2020
    Publication date: September 29, 2022
    Inventors: Daisuke Funamoto, Ryogo Ito, Yuklo Isobe, Toshihiro Ishizaka, Yuji Matsui, Takaharu Yamada
  • Publication number: 20220253476
    Abstract: The present technology relates to a file processing device, a file processing method, and a program that enable association of, for example, an image stored in a file with external data outside the file. A file control unit generates a high efficiency image file format (HEIF) file in which a reserved area is secured that is used to store relationship information related to association of an image stored in the HEIF file with specification information specifying external data that is outside the HEIF file and is to be associated with the image. Furthermore, the file control unit writes the relationship information into the HEIF file by using the reserved area. The present technology can be applied to, for example, a case where a HEIF file is generated and an image stored in the HEIF file is associated with external data later, and the like.
    Type: Application
    Filed: June 5, 2020
    Publication date: August 11, 2022
    Inventors: Daisuke Funamoto, Ryogo Ito, Yukio Isobe, Toshihiro Ishizaka, Yuji Matsul, Takaharu Yamada
  • Publication number: 20220182576
    Abstract: The present technology relates to a file generation device, a file generation method, a file reproduction device, a file reproduction method, and a program capable of associating an image stored is a file with external data outside the file. A file control unit generates an association-type high efficiency image file format (HEIF) file in which an image in an HEIF file compliant with HEIF and specific information that specifies external data outside the HEIF file, the external data to be associated with the image, are stored in association with each other. Furthermore, the file control unit reproduces the association-type HEIF file. The present technology can be applied to a case where an HEIF file is generated or a case where the HEIF file is reproduced.
    Type: Application
    Filed: March 16, 2020
    Publication date: June 9, 2022
    Inventors: Daisuke Funamoto, Ryogo ito, Yukio lsobe, Toshihiro lshizaka, Yuji Matsul, Takaharu Yamada
  • Patent number: 11333939
    Abstract: A display device includes a conventional first auxiliary trunk line formed to be narrow, and a second auxiliary trunk line additionally provided and disposed at the closest position to the periphery of a substrate. Thus, a shift register can be distanced from the periphery of the substrate without increasing a frame area as a whole.
    Type: Grant
    Filed: December 16, 2020
    Date of Patent: May 17, 2022
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Masahiro Yoshida, Isao Ogasawara, Satoshi Horiuchi, Takaharu Yamada
  • Patent number: 11004474
    Abstract: A recording apparatus is disclosed. The recording apparatus includes a data input portion configured to input data, a first moving image signal recording portion configured to record, based on the input data, a first moving image signal having a first image quality attribute, a condition detector configured to detect that the input data satisfies a predetermined condition during recording of the first moving image signal, and a second moving image signal recorder configured to record, based on the input data, a second moving image signal having a second image quality attribute when the condition detector detects that the input data satisfies the predetermined condition.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: May 11, 2021
    Assignee: SONY CORPORATION
    Inventors: Takaharu Yamada, Atsushi Mae
  • Publication number: 20210103176
    Abstract: In the present liquid crystal display device, a conventional first auxiliary capacitance trunk line 430 is formed to be narrow, and a second auxiliary capacitance trunk line 440 is additionally provided and disposed at the closest position to the periphery of a substrate. Thus, a shift register can be distanced from the periphery of the substrate without increasing a frame area as a whole, so that the shift register is not overlaid with a seal material. Moreover, the extent of an area overlaid with a seal material within a wiring area for providing signals to the shift register can be reduced.
    Type: Application
    Filed: December 16, 2020
    Publication date: April 8, 2021
    Inventors: Masahiro YOSHIDA, Isao OGASAWARA, Satoshi HORIUCHI, Takaharu YAMADA
  • Patent number: 10877333
    Abstract: A display device includes a conventional first auxiliary trunk line formed to be narrow, and a second auxiliary trunk line additionally provided and disposed at the closest position to the periphery of a substrate. Thus, a shift register can be distanced from the periphery of the substrate without increasing a frame area as a whole.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: December 29, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Masahiro Yoshida, Isao Ogasawara, Satoshi Horiuchi, Takaharu Yamada
  • Publication number: 20190033648
    Abstract: In the present liquid crystal display device, a conventional first auxiliary capacitance trunk line 430 is formed to be narrow, and a second auxiliary capacitance trunk line 440 is additionally provided and disposed at the closest position to the periphery of a substrate. Thus, a shift register can be distanced from the periphery of the substrate without increasing a frame area as a whole, so that the shift register is not overlaid with a seal material. Moreover, the extent of an area overlaid with a seal material within a wiring area for providing signals to the shift register can be reduced.
    Type: Application
    Filed: October 1, 2018
    Publication date: January 31, 2019
    Inventors: Masahiro YOSHIDA, Isao OGASAWARA, Satoshi HORIUCHI, Takaharu YAMADA
  • Patent number: 10120248
    Abstract: In the present liquid crystal display device, a conventional first auxiliary capacitance trunk line 430 is formed to be narrow, and a second auxiliary capacitance trunk line 440 is additionally provided and disposed at the closest position to the periphery of a substrate. Thus, a shift register can be distanced from the periphery of the substrate without increasing a frame area as a whole, so that the shift register is not overlaid with a seal material. Moreover, the extent of an area overlaid with a seal material within a wiring area for providing signals to the shift register can be reduced.
    Type: Grant
    Filed: January 6, 2016
    Date of Patent: November 6, 2018
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Masahiro Yoshida, Isao Ogasawara, Satoshi Horiuchi, Takaharu Yamada
  • Publication number: 20180025754
    Abstract: A recording apparatus is disclosed. The recording apparatus includes a data input portion configured to input data, a first moving image signal recording portion configured to record, based on the input data, a first moving image signal having a first image quality attribute, a condition detector configured to detect that the input data satisfies a predetermined condition during recording of the first moving image signal, and a second moving image signal recorder configured to record, based on the input data, a second moving image signal having a second image quality attribute when the condition detector detects that the input data satisfies the predetermined condition.
    Type: Application
    Filed: September 29, 2017
    Publication date: January 25, 2018
    Applicant: SONY CORPORATION
    Inventors: Takaharu YAMADA, Atsushi MAE
  • Patent number: 9805765
    Abstract: A recording apparatus is disclosed. The recording apparatus includes a data input portion configured to input data, a first moving image signal recording portion configured to record, based on the input data, a first moving image signal having a first image quality attribute, a condition detector configured to detect that the input data satisfies a predetermined condition during recording of the first moving image signal, and a second moving image signal recorder configured to record, based on the input data, a second moving image signal having a second image quality attribute when the condition detector detects that the input data satisfies the predetermined condition.
    Type: Grant
    Filed: April 8, 2014
    Date of Patent: October 31, 2017
    Assignee: SONY CORPORATION
    Inventors: Takaharu Yamada, Atsushi Mae
  • Patent number: 9766525
    Abstract: In an active matrix substrate, each of at least two auxiliary capacitance electrodes contains a first electrode section and a second electrode section, at least a portion of the first electrode sections and at least a portion of a plurality of source bus lines overlap each other, the second electrode section has two linear sections that branch from the first electrode section and that extend in a second direction, a portion of the region between the two linear sections and at least a portion of the plurality of source bus lines overlap each other, and the first and second electrode sections, which are adjacent and arranged in a first direction, are disposed symmetrically to each other about a reference point that is on a straight line passing through a substantially central portion of respective pixels arranged in the first direction.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: September 19, 2017
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Ryohki Itoh, Masahiro Yoshida, Takaharu Yamada
  • Patent number: 9733538
    Abstract: An embodiment of the present invention provides a TFT array substrate, in which TFT elements and pixel electrodes being correspondingly connected with the TFT elements are arrayed in matrix on an insulating substrate, the TFT array substrate including: gate bus lines made from a first metal material; source bus lines made from a second metal material; pixel electrodes made from a third metal material; a clock wiring made from the first metal material; a branch wiring made from the second metal material; and a connection conductor made from the third metal material, the connection conductor connecting the clock wiring and the branch wiring at a connection part in a periphery area, the connection part having a branch-wiring via hole, which exposes the branch wiring which is covered with the connection conductor, and overlaps the clock wiring at least partly in a plane view.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: August 15, 2017
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Isao Ogasawara, Takaharu Yamada, Masahiro Yoshida, Satoshi Horiuchi, Shinya Tanaka, Tetsuo Kikuchi
  • Publication number: 20170139300
    Abstract: In an active matrix substrate, each of at least two auxiliary capacitance electrodes contains a first electrode section and a second electrode section, at least a portion of the first electrode sections and at least a portion of a plurality of source bus lines overlap each other, the second electrode section has two linear sections that branch from the first electrode section and that extend in a second direction, a portion of the region between the two linear sections and at least a portion of the plurality of source bus lines overlap each other, and the first and second electrode sections, which are adjacent and arranged in a first direction, are disposed symmetrically to each other about a reference point that is on a straight line passing through a substantially central portion of respective pixels arranged in the first direction.
    Type: Application
    Filed: January 31, 2017
    Publication date: May 18, 2017
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Ryohki ITOH, Masahiro YOSHIDA, Takaharu YAMADA
  • Patent number: 9594282
    Abstract: In an active matrix substrate, each of a plurality of auxiliary capacitance electrodes contain a first electrode section and a second electrode section, at least a portion of the first electrode sections and at least a portion of a plurality of source bus lines overlap each other, the second electrode section has two linear sections that branch from the first electrode section and that extend in a second direction, a portion of the region between the two linear sections and at least a portion of the plurality of source bus lines overlap each other, and the first and second electrode sections, which are adjacent and arranged in a first direction, are disposed symmetrically to each other about a reference point that is on a straight line passing through a substantially central portion of respective pixels arranged in the first direction.
    Type: Grant
    Filed: February 19, 2014
    Date of Patent: March 14, 2017
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Ryohki Itoh, Masahiro Yoshida, Takaharu Yamada
  • Publication number: 20160282693
    Abstract: An embodiment of the present invention provides a TFT array substrate, in which TFT elements and pixel electrodes being correspondingly connected with the TFT elements are arrayed in matrix on an insulating substrate, the TFT array substrate including: gate bus lines made from a first metal material; source bus lines made from a second metal material; pixel electrodes made from a third metal material; a clock wiring made from the first metal material; a branch wiring made from the second metal material; and a connection conductor made from the third metal material, the connection conductor connecting the clock wiring and the branch wiring at a connection part in a periphery area, the connection part having a branch-wiring via hole, which exposes the branch wiring which is covered with the connection conductor, and overlaps the clock wiring at least partly in a plane view.
    Type: Application
    Filed: June 3, 2016
    Publication date: September 29, 2016
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Isao OGASAWARA, Takaharu YAMADA, Masahiro YOSHIDA, Satoshi HORIUCHI, Shinya TANAKA, Tetsuo KIKUCHI
  • Patent number: 9385143
    Abstract: An embodiment of the present invention provides a TFT array substrate, in which TFT elements and pixel electrodes being correspondingly connected with the TFT elements are arrayed in matrix on an insulating substrate, the TFT array substrate including: gate bus lines made from a first metal material; source bus lines made from a second metal material; pixel electrodes made from a third metal material; a clock wiring made from the first metal material; a branch wiring made from the second metal material; and a connection conductor made from the third metal material, the connection conductor connecting the clock wiring and the branch wiring at a connection part in a periphery area, the connection part having a branch-wiring via hole, which exposes the branch wiring which is covered with the connection conductor, and overlaps the clock wiring at least partly in a plane view.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: July 5, 2016
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Isao Ogasawara, Takaharu Yamada, Masahiro Yoshida, Satoshi Horiuchi, Shinya Tanaka, Tetsuo Kikuchi
  • Publication number: 20160131933
    Abstract: In the present liquid crystal display device, a conventional first auxiliary capacitance trunk line 430 is formed to be narrow, and a second auxiliary capacitance trunk line 440 is additionally provided and disposed at the closest position to the periphery of a substrate. Thus, a shift register can be distanced from the periphery of the substrate without increasing a frame area as a whole, so that the shift register is not overlaid with a seal material. Moreover, the extent of an area overlaid with a seal material within a wiring area for providing signals to the shift register can be reduced.
    Type: Application
    Filed: January 6, 2016
    Publication date: May 12, 2016
    Inventors: Masahiro YOSHIDA, Isao OGASAWARA, Satoshi HORIUCHI, Takaharu YAMADA