Abstract: A test circuit according to the present invention is so constructed that a memory has a data scramble function and a write pattern can freely be set and changed in a test mode. Each of data lines is a pair of complementary lines. A data scrambler and a data descrambler are arranged on the input and output sides, respectively. A latch circuit receives some of row addresses and supplies eight pairs of scramble signals CHNG to the data scrambler. An ENTRY/EXIT circuit outputs a TEST signal for selecting the normal and test modes. The latch circuit controls the modes in response to the TEST signal. In the test mode, the data, the data scrambler scrambles write data of the data lines in response to a scramble signal, and the data descrambler descrambles read data read out to the data lines from each memory cell in which the write data is stored, in response to the scramble signal, to return the data to the state prior to the scramble.