Abstract: A power-down circuit for saving operational power dissipation of a dynamic MOS integrated circuit during idling conditions. A clock divider generates a divided clock signal in response to an internal clock signal inputted thereto. The divided signal is synchronized with the internal clock signal and has a repetition rate which is slower than that of the internal clock signal. A control circuit delivers the control signal when a triggering signal is inputted thereto. A clock selecting circuit transfers either the internal clock signal or the divided clock signal to the dynamic MOS integrated circuit in response to the control signal.