Patents by Inventor Takahide Baba
Takahide Baba has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8344776Abstract: Provided is a memory interface circuit connected to a memory device that outputs a first data signal, and including: a first delay unit delaying a first strobe signal outputted from the memory device by a first delay amount to generate a first delayed strobe signal; a first data latch unit latching the first data signal as a first latched data signal in synchronization with the first delayed strobe signal; a first range calculating unit calculating a first delay range width that is a width of a range of values of the first delay amount which allow the first data latch unit to correctly latch the first data signal as the first latched data signal; and a drive capability setting unit adjusting the drive capability of the memory device so as to widen the first delay range width.Type: GrantFiled: May 17, 2012Date of Patent: January 1, 2013Assignee: Panasonic CorporationInventor: Takahide Baba
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Publication number: 20120229186Abstract: Provided is a memory interface circuit connected to a memory device that outputs a first data signal, and including: a first delay unit delaying a first strobe signal outputted from the memory device by a first delay amount to generate a first delayed strobe signal; a first data latch unit latching the first data signal as a first latched data signal in synchronization with the first delayed strobe signal; a first range calculating unit calculating a first delay range width that is a width of a range of values of the first delay amount which allow the first data latch unit to correctly latch the first data signal as the first latched data signal; and a drive capability setting unit adjusting the drive capability of the memory device so as to widen the first delay range width.Type: ApplicationFiled: May 17, 2012Publication date: September 13, 2012Applicant: PANASONIC CORPORATIONInventor: Takahide BABA
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Publication number: 20110176372Abstract: The memory interface includes: a first data latch unit that delays a strobe signal from a memory device, through a first variable delay unit and reads the strobe signal as a first data signal; and a second data latch unit that delays the same strobe signal through the second variable delay unit and reads the strobe signal as a second data signal. The memory interface uses the data read by the first data latch unit in a normal memory access operation, detects a boundary of the delay amount by comparing the data with the data read by the second data latch unit, and reflects the boundary on the delay amount of the first variable delay unit. Thereby, the delay amount can be corrected without suspending the normal memory access operation.Type: ApplicationFiled: March 31, 2011Publication date: July 21, 2011Applicant: PANASONIC CORPORATIONInventors: Takahide BABA, Isao KAWAMOTO, Daisuke MURAKAMI, Yuji TAKAI
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Patent number: 7885133Abstract: A clock enable (CKE) control circuit (112) is provided between a memory control circuit (111) and a SDRAM (120). When a system is in, e.g., a sleep state, the CKE control circuit (112) controls a CKE signal outputted to the SDRAM (120) such that it is fixed to a Low level. As a result, it is possible to halt a power supply provided to the memory control circuit (111), while maintaining the low-power-consumption mode of the SDRAM (120), so that power consumption resulting from a leakage current is suppressed. In addition, it becomes also possible to reset the memory control circuit (111), while maintaining the low-power-consumption mode of the SDRAM (120).Type: GrantFiled: October 19, 2006Date of Patent: February 8, 2011Assignee: Panasonic CorporationInventors: Daisuke Murakami, Yuji Takai, Takahide Baba
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Patent number: 7860940Abstract: A transmission cancellation section is provided on a bus connecting a master and a slave. During a reset of the master, the transmission cancellation section blocks the bus so that an invalid command flowing on the bus does not reach the slave and executes, instead of the master stopped by the reset operation, generation of data which corresponds to an access request command already output to the slave and is to be sent to the slave and receiving of data from the slave.Type: GrantFiled: March 28, 2008Date of Patent: December 28, 2010Assignee: Panasonic CorporationInventors: Yuki Soga, Daisuke Murakami, Takahide Baba, Yuji Takai, Yasuo Nishioka
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Publication number: 20090282270Abstract: A clock enable (CKE) control circuit (112) is provided between a memory control circuit (111) and a SDRAM (120). When a system is in, e.g., a sleep state, the CKE control circuit (112) controls a CKE signal outputted to the SDRAM (120) such that it is fixed to a Low level. As a result, it is possible to halt a power supply provided to the memory control circuit (111), while maintaining the low-power-consumption mode of the SDRAM (120), so that power consumption resulting from a leakage current is suppressed. In addition, it becomes also possible to reset the memory control circuit (111), while maintaining the low-power-consumption mode of the SDRAM (120).Type: ApplicationFiled: October 19, 2006Publication date: November 12, 2009Applicant: PANASONIC CORPORATIONInventors: Daisuke Murakami, Yuji Takai, Takahide Baba
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Patent number: 7472213Abstract: Bandwidth information including a plurality of slots each having highest priority order information for arbitrating access conflict, and priority master information for specifying, as a priority master, one or more of a plurality of masters whose latency in accessing a memory serving as a shared resource is desired to be reduced are included as arbitration information. When an arbitration section arbitrates access conflict while switching the slots in the bandwidth information at each of predetermined arbitration timings, if there is an access request from the priority master specified in the priority master information, the arbitration section changes the sequence of the slots in the bandwidth information so as to allow the priority master to access the memory with priority.Type: GrantFiled: October 31, 2007Date of Patent: December 30, 2008Assignee: Panasonic CorporationInventors: Toshihiro Fukuyama, Yuji Takai, Isao Kawamoto, Takahide Baba, Daisuke Murakami, Yoshiharu Watanabe
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Publication number: 20080244029Abstract: A transmission cancellation section is provided on a bus connecting a master and a slave. During a reset of the master, the transmission cancellation section blocks the bus so that an invalid command flowing on the bus does not reach the slave and executes, instead of the master stopped by the reset operation, generation of data which corresponds to an access request command already output to the slave and is to be sent to the slave and receiving of data from the slave.Type: ApplicationFiled: March 28, 2008Publication date: October 2, 2008Inventors: Yuki Soga, Daisuke Murakami, Takahide Baba, Yuji Takai, Yasuo Nishioka
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Publication number: 20080098153Abstract: A memory access controller includes: an access request bank analyzer which generates access request bank information indicative of a bank of a memory to be accessed according to a memory access request signal; a bank use state information holder for holding the access request bank information for a predetermined period to use the held information as bank use state information; and an access permission signal generator for generating, based on the access request bank information and the bank use state information, an access permission signal which is to be used for controlling whether or not to accept a subsequent memory bank access. The bank use state information regarding an access-permitted memory bank is updated according to the access information, such as transfer direction information, access unit information, memory initialization information, etc.Type: ApplicationFiled: August 22, 2007Publication date: April 24, 2008Inventors: Yasuo Nishioka, Takahide Baba, Seiji Horii, Yoshiharu Watanabe
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Patent number: 7350004Abstract: Bandwidth information including a plurality of slots each having highest priority order information for arbitrating access conflict, and priority master information for specifying, as a priority master, one or more of a plurality of masters whose latency in accessing a memory serving as a shared resource is desired to be reduced are included as arbitration information. When an arbitration section arbitrates access conflict while switching the slots in the bandwidth information at each of predetermined arbitration timings, if there is an access request from the priority master specified in the priority master information, the arbitration section changes the sequence of the slots in the bandwidth information so as to allow the priority master to access the memory with priority.Type: GrantFiled: February 15, 2005Date of Patent: March 25, 2008Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Toshihiro Fukuyama, Yuji Takai, Isao Kawamoto, Takahide Baba, Daisuke Murakami, Yoshiharu Watanabe
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Publication number: 20080065801Abstract: Bandwidth information including a plurality of slots each having highest priority order information for arbitrating access conflict, and priority master information for specifying, as a priority master, one or more of a plurality of masters whose latency in accessing a memory serving as a shared resource is desired to be reduced are included as arbitration information. When an arbitration section arbitrates access conflict while switching the slots in the bandwidth information at each of predetermined arbitration timings, if there is an access request from the priority master specified in the priority master information, the arbitration section changes the sequence of the slots in the bandwidth information so as to allow the priority master to access the memory with priority.Type: ApplicationFiled: October 31, 2007Publication date: March 13, 2008Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Toshihiro Fukuyama, Yuji Takai, Isao Kawamoto, Takahide Baba, Daisuke Murakami, Yoshiharu Watanabe
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Publication number: 20060155903Abstract: A bus arbitration part for arbitrating access requests from bus masters includes an arbitration history management section that records absence of an access request from any bus master at a given basic arbitration timing. Based on this record, an access request arbitration section issues access permission for an access request issued after the given basic arbitration timing without a wait for the next basic arbitration timing.Type: ApplicationFiled: November 23, 2005Publication date: July 13, 2006Inventors: Yuki Soga, Takahide Baba, Yuji Takai, Daisuke Murakami
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Patent number: 7032046Abstract: A resource management device of the present invention, used in a system where at least one bus master is connected to each of a plurality of buses, includes: a bus arbitration section for arbitrating an amount of access to be made from the buses to a shared resource; an arbitration information management section for managing, as bus arbitration information, a bus priority order and a highest access priority pattern for ensuring a predetermined access bandwidth to the shared resource for each bus for an arbitration operation by the bus arbitration section; and a resource control section for controlling, based on characteristics of the shared resource, an access to the shared resource from the bus whose access request has been granted by the bus arbitration section. Thus, it is possible to guarantee a minimum bandwidth for access to the shared resource for each of the plurality of bus masters.Type: GrantFiled: September 30, 2003Date of Patent: April 18, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Seiji Horii, Yuji Takai, Takahide Baba, Yoshiharu Watanabe, Daisuke Murakami, Tetsuji Kishi
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Publication number: 20060047874Abstract: To manage accesses from a plurality of masters to a shared resource, a plurality of command registers of each holding an access command received from any of the masters and a plurality of address registers of each holding a register number identifying a command register holding a valid access command, are provided. To rearrange the issuing order of access commands, register numbers held in the address registers are rearranged.Type: ApplicationFiled: August 5, 2005Publication date: March 2, 2006Inventors: Yoshiharu Watanabe, Yuji Takai, Isao Kawamoto, Takahide Baba, Daisuke Murakami, Toshihiro Fukuyama
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Publication number: 20050204085Abstract: Bandwidth information including a plurality of slots each having highest priority order information for arbitrating access conflict, and priority master information for specifying, as a priority master, one or more of a plurality of masters whose latency in accessing a memory serving as a shared resource is desired to be reduced are included as arbitration information. When an arbitration section arbitrates access conflict while switching the slots in the bandwidth information at each of predetermined arbitration timings, if there is an access request from the priority master specified in the priority master information, the arbitration section changes the sequence of the slots in the bandwidth information so as to allow the priority master to access the memory with priority.Type: ApplicationFiled: February 15, 2005Publication date: September 15, 2005Inventors: Toshihiro Fukuyama, Yuji Takai, Isao Kawamoto, Takahide Baba, Daisuke Murakami, Yoshiharu Watanabe
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Publication number: 20050066097Abstract: A resource management apparatus comprises an information selection unit having an operation speed different to an operation speed of a common resource and selecting from information transferred from a plurality of bus masters, a buffer unit for storing the information selected by the information selection unit, and a timing adjustment unit for controlling timings of the information selections in the information selection unit. The information selection unit selects the information comprised of a command and data transferred from any of the plurality of bus masters to the common resource. The timing adjustment unit controls the timings of the information selections in the information selection unit so that the sum of time required for selecting a plurality of predetermined volumes of information in the information selection unit and the sum of processing time in the common resource are substantially equal to each other.Type: ApplicationFiled: August 30, 2004Publication date: March 24, 2005Inventors: Isao Kawamoto, Seiji Horii, Yuji Takai, Tetsuji Kishi, Takahide Baba, Daisuke Murakami, Yoshiharu Watanabe, Toshihiro Fukuyama
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Publication number: 20040073730Abstract: A resource management device of the present invention, used in a system where at least one bus master is connected to each of a plurality of buses, includes: a bus arbitration section for arbitrating an amount of access to be made from the buses to a shared resource; an arbitration information management section for managing, as bus arbitration information, a bus priority order and a highest access priority pattern for ensuring a predetermined access bandwidth to the shared resource for each bus for an arbitration operation by the bus arbitration section; and a resource control section for controlling, based on characteristics of the shared resource, an access to the shared resource from the bus whose access request has been granted by the bus arbitration section. Thus, it is possible to guarantee a minimum bandwidth for access to the shared resource for each of the plurality of bus masters.Type: ApplicationFiled: September 30, 2003Publication date: April 15, 2004Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Seiji Horii, Yuji Takai, Takahide Baba, Yoshiharu Watanabe, Daisuke Murakami, Tetsuji Kishi