Patents by Inventor Takahide Ishikawa

Takahide Ishikawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10302155
    Abstract: A rotation transmission device includes an electromagnetic clutch including an armature, a rotor having an outer tubular portion and an inner tubular portion, and an electromagnet. A bearing support tube is provided at the outer end surface of a core supporting an electromagnetic coil of the electromagnet. A bearing is mounted in the bearing support tube so as to be axially fixed in position and not to be pulled out of the bearing support tube. The small-diameter tubular portion is provided at the end of the inner tubular portion of the rotor, and press-fitted in the bearing such that the rotor and the electromagnet form a unit.
    Type: Grant
    Filed: March 26, 2015
    Date of Patent: May 28, 2019
    Assignee: NTN CORPORATION
    Inventors: Naotsugu Kitayama, Shintaro Ishikawa, Koji Sato, Takahide Saito
  • Patent number: 6998615
    Abstract: In a method of evaluating a piezoelectric field, non-destructive spectrometry of piezoelectric fields is performed in a semiconductor heterojunction using a technique different from PR spectroscopy. In the method, at first, first and second absorption spectra are measured by irradiating the sample with infrared light at first and second angles, respectively. Then, a peak position of an absorption band having incident-angle dependent intensity is specified, based on the first and second absorption spectra. Thus, the piezoelectric field strength is obtained using a relationship between the piezoelectric field and an electron energy level corresponding to the peak position.
    Type: Grant
    Filed: February 2, 2004
    Date of Patent: February 14, 2006
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hideo Takeuchi, Yoshitsugu Yamamoto, Takahide Ishikawa
  • Patent number: 6911837
    Abstract: The present method includes steps of: discharging a droplet of fluid containing fine particles with electric characteristics from an inkjet nozzle onto the microwave integrated circuit formed on a substrate; forming a coat of the fine particles having electric characteristics on the substrate; measuring electric characteristics of the microwave integrated circuit using a probe of a circuit evaluation apparatus before and after forming the coat; and adjusting the electric characteristics of the microwave integrated circuit, so that forming the coat at a desired location on the upper surface of the circuit substrate by scanning an aim of the inkjet nozzle against the circuit substrate enables the microwave integrated circuit to meet the specification.
    Type: Grant
    Filed: July 19, 2004
    Date of Patent: June 28, 2005
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Takahide Ishikawa, Yoshitsugu Yamamoto, Tetsuo Kunii, Satoshi Suzuki, Hirotaka Amasuga
  • Publication number: 20050046435
    Abstract: The present method includes steps of: discharging a droplet of fluid containing fine particles with electric characteristics from an inkjet nozzle onto the microwave integrated circuit formed on a substrate; forming a coat of the fine particles having electric characteristics on the substrate; measuring electric characteristics of the microwave integrated circuit using a probe of a circuit evaluation apparatus before and after forming the coat; and adjusting the electric characteristics of the microwave integrated circuit, so that forming the coat at a desired location on the upper surface of the circuit substrate by scanning an aim of the inkjet nozzle against the circuit substrate enables the microwave integrated circuit to meet the specification.
    Type: Application
    Filed: July 19, 2004
    Publication date: March 3, 2005
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Takahide Ishikawa, Yoshitsugu Yamamoto, Tetsuo Kunii, Satoshi Suzuki, Hirotaka Amasuga
  • Publication number: 20040155194
    Abstract: In a method of evaluating a piezoelectric field, a non-destructive spectrometry of piezoelectric fields is performed in a semiconductor heterojunction using a technique different from PR spectroscopy. In the method, at first, first and second absorption spectra are measured by irradiating infrared light to a sample with first and second angles, respectively. Then, a peak position of an absorption band having incident-angle dependent intensity is specified based on the first and second absorption spectra. Thus, the piezoelectric field strength is obtained based on an equation of energy level. The equation represents a relationship between the piezoelectric field and an electron energy level corresponding to the peak position.
    Type: Application
    Filed: February 2, 2004
    Publication date: August 12, 2004
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hideo Takeuchi, Yoshitsugu Yamamoto, Takahide Ishikawa
  • Patent number: 6271619
    Abstract: A piezoelectric thin film device which is composed mainly of a substrate, a piezoelectric thin film formed on the substrate, and thin film electrodes formed on both the upper and lower surfaces of the thin film. The thin film is resonated by applying an AC voltage across the electrodes. A substrate removed section is formed by partially or entirely removing the substrate below the thin film and opened to both the front and rear surfaces of the substrate through openings so as to relieve the pressure variation in the substrate removed section below a resonant structure.
    Type: Grant
    Filed: November 12, 1999
    Date of Patent: August 7, 2001
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Akira Yamada, Chisako Maeda, Toshio Umemura, Fusaoki Uchikawa, Koichiro Misu, Shusou Wadaka, Takahide Ishikawa
  • Patent number: 5932926
    Abstract: A microwave semiconductor integrated circuit having high isolation includes a wiring-side substrate including a transmission line in slots at a surface; an element-side substrate having an active element on a surface, the transmission line being embedded in the wiring-side substrate; and metal bumps electrically connecting the transmission line embedded in the wiring-side substrate to electrodes of the active element on the element-side substrate. Therefore, a connection between a transmission line and electrodes of an element, such as an FET or the like, can be easily realized without being affected by a difference in positional level between the transmission line and the electrodes. In addition, the element on the element-side substrate is not adversely affected by the subsequent fabrication of the slots and wiring layers and, therefore, the reliability of the integrated circuit is not adversely affected.
    Type: Grant
    Filed: February 5, 1997
    Date of Patent: August 3, 1999
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Takaya Maruyama, Takahide Ishikawa, Noriyuki Tanino
  • Patent number: 5812364
    Abstract: An MIM capacitor includes a lower electrode; a first insulating film disposed on the lower electrode; a second insulating film disposed on the first insulating film and having a first opening exposing a portion of the surface of the first insulating film on the lower electrode, the first opening having a perimeter; a third insulating film disposed on the second insulating film and having a second opening exposing a portion of the surface of the second insulating film, the second opening having a perimeter that surrounds the perimeter of the first opening on the second insulating film; and an upper electrode disposed on the first insulating film through the first opening and extending onto the second insulating film.
    Type: Grant
    Filed: January 15, 1997
    Date of Patent: September 22, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tomoki Oku, Takahide Ishikawa
  • Patent number: 5652557
    Abstract: A transmission line including a dielectric or semi-insulating substrate; a groove in the substrate; a metallization film disposed on the bottom surface of the groove; a dielectric filling the groove and making contact with the metallization film; a wiring conductor film disposed on the dielectric; and a grounding metallization film disposed on the rear surface of the substrate. Excellent confinement of electromagnetic waves is achieved and electromagnetic wave interference between two neighboring lines is extremely small, realizing a high density arrangement of transmission lines and a compact and lightweight microwave/millimeter wave integrated circuit. Higher modes of electromagnetic wave propagation are avoided by controlling the thickness of the dielectric filling the groove while the thickness of the substrate remains arbitrary, thereby improving production yield and reliability.
    Type: Grant
    Filed: October 17, 1995
    Date of Patent: July 29, 1997
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Takahide Ishikawa
  • Patent number: 5434094
    Abstract: FET devices according to the invention are made by etching separation grooves and the via-holes from the front surface of the substrate. Thereafter, the thickness of the substrate is reduced from the rear surface to expose the plating in the via-holes and separation grooves. A rear surface electrode and a plated heat sink are sequentially deposited on the rear surface of the thinned substrate. The devices are divided from a wafer by etching and/or severing along the separation grooves and at opposed locations along the plated heat sink.
    Type: Grant
    Filed: April 8, 1994
    Date of Patent: July 18, 1995
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Michihiro Kobiki, Masahiro Yoshida, Takahide Ishikawa
  • Patent number: 5429994
    Abstract: In a method of manufacturing a semiconductor device, a metal film including a metal element is formed on a wiring base layer by ion beam assisted CVD, more specifically, by selectively irradiating a region of the wiring base layer with a focused ion beam while blowing an organic metal gas containing the metal element onto the region irradiated by the ion beam. Thereafter, a low-resistance metal layer is formed on the metal film by electroless plating. Therefore, a metal wiring of low resistivity with a predetermined pattern is formed without a photolithographic process using a resist and also without sputtering or selective etching of the metal film. Consequently, manufacturing costs of a semiconductor device are significantly reduced.
    Type: Grant
    Filed: July 21, 1994
    Date of Patent: July 4, 1995
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Takahide Ishikawa
  • Patent number: 5324981
    Abstract: A high power FET device includes a plated heat sink, a rear surface electrode disposed between a substrate and the heat sink, a via-hole extending through the substrate and containing a metal plating for electrically connecting the rear surface electrode and an element, such as the source electrode, of the FET device. A metallic layer extending from the rear surface to the front surface of the device protects the side walls of the substrate during handling. The side wall protection layer extends onto portions of the front surface of the substrate as a measurement electrode. The arrangement gives access to the source, drain, and gate electrodes of the device from the front surface for measuring the electrical characteristics of the device while it is still part of a wafer containing a large number of devices. Each device includes a separation groove outwardly spaced from the device and containing a metallic layer which becomes the side wall protection layer after dicing.
    Type: Grant
    Filed: April 14, 1993
    Date of Patent: June 28, 1994
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Michihiro Kobiki, Masahiro Yoshida, Takahide Ishikawa
  • Patent number: 5302554
    Abstract: According to a method for producing semiconductor chips, grooves serving as dicing lines are formed in a front surface of a semiconductor wafer, the semiconductor wafer is ground from the rear surface to a prescribed thickness, leaving portions of the wafer opposite the grooves, a feeding layer is formed on the ground rear surface of the wafer, a metal layer for heat radiation is formed on the feeding layer, a dicing tape is applied to the metal layer, and the wafer and the feeding layer are diced along the dicing lines, resulting in a plurality of semiconductor chips. Therefore, the strength of the wafer is increased because portions of the wafer remain at the dicing lines, preventing curvature of the wafer.
    Type: Grant
    Filed: August 11, 1992
    Date of Patent: April 12, 1994
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Takuo Kashiwa, Takahide Ishikawa, Yoshihiro Notani
  • Patent number: 5275958
    Abstract: According to a method for producing semiconductor chips, first grooves are formed in a semiconductor wafer at a front surface, dividing the semiconductor water into a plurality of regions, each region including a single device or an integrated circuit; a first metallization layer is formed in the first grooves; the semiconductor wafer is thinned to a desired thickness from the rear surface of the wafer; second grooves are formed in the semiconductor wafer at the rear surface at positions opposite the first grooves, exposing the first metallization layer; a second metallization layer is formed in the second grooves; a metal layer for heat radiation is formed on the rear surface of the wafer but not on the second metallization layer; and the first and second metallization layers in the first grooves are cut with a dicing blade to produce a plurality of semiconductor chips.
    Type: Grant
    Filed: January 13, 1993
    Date of Patent: January 4, 1994
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Takahide Ishikawa
  • Patent number: 5270228
    Abstract: A method of fabricating a field effect transistor in which the gate electrode is formed in a multiple step recess including a first recess located on one level and a second recess located on a lower level. The second, narrower recess is nested in the first, wider recess. The method is initiated by growing a first semiconductor layer of a low etch rate on a semiconductor substrate. Then, a second semiconductor layer of a high etch rate is grown on the first semiconductor layer. A resist film having an opening in a selected location is formed on the second semiconductor layer. Using this resist film as a mask, the semiconductor layers are selectively etched. The gate electrode is formed at the bottom of the multiple step recess created by the etching.
    Type: Grant
    Filed: August 15, 1991
    Date of Patent: December 14, 1993
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Takahide Ishikawa
  • Patent number: 5177026
    Abstract: A compound semiconductor MIS FET includes a channel layer produced on a semi-insulating substrate with an intervening buffer layer, source and drain electrodes produced directly on a predetermined region of the channel layer, and a Schottky barrier gate electrode produced on the channel layer between the source and drain ohmic electrodes and on an undoped semiconductor layer. A production method for such a compound semiconductor MIS FET includes removing by etching undoped semiconductor layer at source and drain electrode production regions to expose a channel layer existing therebelow before producing the source and drain electrodes, and producing ohmic electrodes on the exposed channel layer and producing a Schottky barrier gate electrode between the source and drain electrodes on the undoped layer.
    Type: Grant
    Filed: April 17, 1991
    Date of Patent: January 5, 1993
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Takahide Ishikawa
  • Patent number: 5045503
    Abstract: A microwave monolithic integrated circuit comprising a GaAs substrate having upper and lower opposed surfaces, an active region and at least one passive region produced on the upper surface of the substrate, and a heat sink produced on the lower surface of the substrate, wherein the substrate thickness beneath the active region is smaller than the substrate thickness beneath at least one passive region, thereby disposing the heat sink near the active region to improve heat dissipation therefrom. The active region and the passive regions are separated by intermediate areas and the substrate thickness beneath the intermediate areas is smaller than the substrate thickness beneath the active region such that the heat sink at least partially surrounds the substrate beneath the active region.
    Type: Grant
    Filed: June 26, 1990
    Date of Patent: September 3, 1991
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Michihiro Kobiki, Masahiro Yoshida, Takahide Ishikawa
  • Patent number: 4990973
    Abstract: A method of producing MMIC's and the MMIC thus produced having a reproducible quiescent operating point from lot to lot under the same bias conditions. The source to drain saturation current of the amplifier MESFET in the MMIC can vary from lot to lot if the depth of the gate recess varies from lot to lot. As a result, the quiescent operating point of the amplifier under the same bias conditions can vary from lot to lot. A compensated gate bias source, preferably in the form of an extra MESFET on the MMIC, is fabricated at the same time as the amplifier MESFET and thus has a gate recess having a depth which precisely matches that of the amplifier MESFET. The extra MESFET is connected as a compensated gate bias source and has a resistance which is a function of the depth of the gate recess and thus compensates the quiescent operating point of the amplifier MESFET.
    Type: Grant
    Filed: November 15, 1989
    Date of Patent: February 5, 1991
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Takahide Ishikawa, Kazuhiko Nakahara
  • Patent number: 4956697
    Abstract: A microwave monolithic integrated circuit comprising a GaAs substrate having upper and lower opposed surfaces, an active region and at least one passive region produced on the upper surface of the substrate, and a heat sink produced on the lower surface of the substrate, wherein the substrate thickness beneath the active region is smaller than the substrate thickness beneath at least one passive region, thereby disposing the heat sink near the active region to improve heat dissipation therefrom. The active region and the passive regions are separated by intermediate areas and the substrate thickness beneath the intermediate areas is smaller than the substrate thickness beneath the active region such that the heat sink at least partially surrounds the substrate beneath the active region.
    Type: Grant
    Filed: September 30, 1988
    Date of Patent: September 11, 1990
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Michihiro Kobiki, Masahiro Yoshida, Takahide Ishikawa
  • Patent number: 4921814
    Abstract: A method of producing MMIC's and the MMIC thus produced having a reproducible quiescent operating point from lot to lot under the same bias conditions. The source to drain saturation current of the amplifier MESFET in the MMIC can vary from lot to lot if the depth of the gate recess varies from lot to lot. As a result, the quiescent operating point of the amplifier under the same bias conditions can vary from lot to lot. A compensated gate bias source, preferably in the form of an extra MESFET on the MMIC, is fabricated at the same time as the amplifier MESFET and thus has a gate recess having a depth which precisely matches that of the amplifier MESFET. The extra MESFET is connected as a compensated gate bias source and has a resistance which is a function of the depth of the gate recess and thus compensates the quiescent operating point of the amplifier MESFET.
    Type: Grant
    Filed: December 22, 1988
    Date of Patent: May 1, 1990
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Takahide Ishikawa, Kazuhiko Nakahara