Abstract: According to one embodiment, a memory system includes a plurality of nonvolatile semiconductor memories including a plurality of memory cell transistors for holding data, and holding position information indicating a position of a defective memory cell transistor incapable of normally holding data and a position of a substitute portion for the defective memory cell transistor.

Abstract: According to one embodiment, a semiconductor integrated circuit includes an input register which latches, by a second unit, data which are read from a memory cell array by a first unit, a bit state-counter which counts a bit state of the data latched in the input register, a frame size-setup register which latches the first unit, an input data-counter which detects whether or not a total number of the data input to the input register reaches to the first unit, an accumulation circuit which accumulate a value counted by the bit state-counter, a threshold value-register which latches a threshold value for detecting whether or not an erase area of the memory cell array is accessed, a comparison circuit which compares an accumulated value of the accumulation circuit and the threshold value with each other, and a product storage-register which latches a result of the comparison circuit.

Abstract: A controller includes an instruction table memory, a program counter, a first decoder, and a first executing unit. The instruction table memory stores an instruction code obtained by coding a sequence to access a nonvolatile semiconductor memory. A read address in the instruction table memory is set to the program counter. The first decoder decodes the instruction code read from the instruction table memory to output a first decode signal. The first executing unit executes access to the nonvolatile semiconductor memory on the basis of the first decode signal output from the first decoder.

Abstract: According to one embodiment, a semiconductor integrated circuit includes an input register which latches, by a second unit, data which are read from a memory cell array by a first unit, a bit state-counter which counts a bit state of the data latched in the input register, a frame size-setup register which latches the first unit, an input data-counter which detects whether or not a total number of the data input to the input register reaches to the first unit, an accumulation circuit which accumulate a value counted by the bit state-counter, a threshold value-register which latches a threshold value for detecting whether or not an erase area of the memory cell array is accessed, a comparison circuit which compares an accumulated value of the accumulation circuit and the threshold value with each other, and a product storage-register which latches a result of the comparison circuit.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory, a first buffer configured to temporarily store data transferred from the nonvolatile memory, a correction circuit configured to correct an error of data transferred from the first buffer, a second buffer configured to temporarily store data transferred from the correction circuit, a bus configured to receive data transferred from the second buffer, a command sequencer group configured to issue commands for data transfer between the nonvolatile memory and the bus, a command decoder group configured to decode the commands, and generate control signals for controlling data transfer, a CPU connected to the bus, and an interrupt circuit configured to generate an interrupt in the CPU if a read error occurs because of an error correction failure. The command sequencer group continues data transfer from the nonvolatile memory even when an interrupt occurs because of the read error.

Abstract: A memory system includes a nonvolatile memory configured to store data, a first buffer configured to temporarily store data from the nonvolatile memory, a correction circuit configured to correct an error of data from the first buffer, a second buffer configured to temporarily store data from the correction circuit, a bus configured to receive data from the second buffer, a command sequence unit configured to issue a command for data transfer between modules, the modules including the first buffer, the correction circuit and the second buffer, and a command decode unit configured to decode the command and to generate a control signal for controlling the data transfer.

Abstract: A controller includes an instruction table memory, a program counter, a first decoder, and a first executing unit. The instruction table memory stores an instruction code obtained by coding a sequence to access a nonvolatile semiconductor memory. A read address in the instruction table memory is set to the program counter. The first decoder decodes the instruction code read from the instruction table memory to output a first decode signal. The first executing unit executes access to the nonvolatile semiconductor memory on the basis of the first decode signal output from the first decoder.