Abstract: A method for updating two or more regions of the display area of a bistable, electro-optic display device comprises selecting at least one first waveform for at least one pixel of a first region; (b) selecting at least one second waveform for at least one pixel of a second region; (c) updating the first region by generating and providing the first waveform to the at least one pixel of the first region; and (d) updating the second region by generating and providing the second waveform to the at least one pixel of the second region, wherein the first and second updates at least partially coincide in time. The first waveform is selected from a first drive scheme for use in a first update mode having a first period. The second waveform is selected from second a drive scheme for use in a second update mode having a second period.

Abstract: A data structure for use in controlling a bistable electro-optic display having a plurality of pixels comprises a pixel data storage area storing, for each pixel of the display, data representing initial and desired final states of the pixel, and a drive scheme index number representing the drive scheme to be applied; and a drive scheme storage area storing data representing at least all the drive schemes denoted by the drive scheme index numbers stored in the pixel data storage area. A corresponding method of driving a bistable electro-optic display using such a data structure is also provided.

Abstract: A method for updating two or more regions of the display area of a bistable, electro-optic display device comprises selecting at least one first waveform for at least one pixel of a first region; (b) selecting at least one second waveform for at least one pixel of a second region; (c) updating the first region by generating and providing the first waveform to the at least one pixel of the first region; and (d) updating the second region by generating and providing the second waveform to the at least one pixel of the second region, wherein the first and second updates at least partially coincide in time. The first waveform is selected from a first drive scheme for use in a first update mode having a first period. The second waveform is selected from second a drive scheme for use in a second update mode having a second period.

Abstract: A data structure for use in controlling a bistable electro-optic display having a plurality of pixels comprises a pixel data storage area storing, for each pixel of the display, data representing initial and desired final states of the pixel, and a drive scheme index number representing the drive scheme to be applied; and a drive scheme storage area storing data representing at least all the drive schemes denoted by the drive scheme index numbers stored in the pixel data storage area. A corresponding method of driving a bistable electro-optic display using such a data structure is also provided.

Abstract: A system is provided to increase the accessibility of registers and memories in a user's design undergoing functional verification in a hardware-assisted design verification system. A packet-based protocol is used to perform data transfer operations between a host workstation and a hardware accelerator for loading data to and unloading data from the registers and memories in a target design under verification (DUV) during logic simulation. The method and apparatus synthesizes interface logic into the DUV to provide for greater access to the registers and memories in the target DUV which is simulated with the assistance of the hardware accelerator.

Abstract: In a prefetch buffering system and method, a pool of prefetch buffers are organized in such a manner that there is a tight connection between the buffer pool and the data streams of interest. In this manner, efficient prefetching of data from memory is achieved and the amount of required buffer space is reduced. A memory control system controls the reading of data from a memory. A plurality of buffers buffer data read from the memory. A buffer assignment unit assigns a plurality of data streams to the plurality of buffers. The buffer assignment unit assigns to each data stream a primary buffer and a secondary buffer of the plurality of buffers, such that upon receiving a data request from a first data stream, the primary buffer assigned to the first data stream contains fetch data of the data request and the secondary buffer assigned to the first data stream contains prefetch data of the data request.

Abstract: A plurality of identical rendering pipelines are connected in parallel to read an array of voxels and to write an array of pixels. Each pipeline processes one voxel in one processing cycle of the pipelines. Each pipeline includes a plurality of serially connected different stages. The stages can include interpolation, classification, gradient estimation, illumination, and compositing stages. Interfaces connect identical stages in adjacent pipelines as one-way rings to communicate information associated with spatially adjacent voxels, and delay buffers connected parallel to particular stages communicate information associated with temporally adjacent voxels.

Abstract: A volume rendering integrated circuit includes a plurality of interconnected pipelines having stages operating in parallel. The stages of the pipelines are interconnected in a ring, with data being passed in only one direction around the ring. The volume integrated circuit also includes a render controller for controlling the flow of volume data to and from the pipelines and for controlling rendering operations of the pipelines. The integrated circuit may further include interfaces for coupling the integrated circuit to various storage devices and to a host computer.

Abstract: A system is provided to increase the accessibility of registers and memories in a user's design undergoing functional verification in a hardware-assisted design verification system. A packet-based protocol is used to perform data transfer operations between a host workstation and a hardware accelerator for loading data to and unloading data from the registers and memories in a target design under verification (DUV) during logic simulation. The method and apparatus synthesizes interface logic into the DUV to provide for greater access to the registers and memories in the target DUV which is simulated with the assistance of the hardware accelerator.

Abstract: A volume rendering system re-samples voxels read from a voxel memory to generate samples along perspective rays cast from a center of projection using a level of detail value. Color computations are performed with the samples to produce pixels for a baseplane image. The level of detail is computed, at each plane of samples perpendicular to a principal viewing axis, from the current sample position and the distance between the center of projection and the baseplane; the principal viewing axis is the coordinate axis in a rendered volume most parallel with a viewing vector. The level of detail provides a measure of the distance between two neighboring perspective rays at each plane and is used to determine the number of voxels and weights for these voxels required to compute a single sample at each plane. Multi-resolution datasets prepared for different levels of details are used to simplify the resampling operation by limiting the number of voxels required to compute a single sample.

Abstract: A system is provided to enhance the capability of a display system which format digital images of different types from multiple input data streams for a high-resolution screen of arbitrary shape and size, with the display system adapted to receive independent data streams from different data sources at the same time and control how and where the images from the data streams are presented on the screen in a type-independent manner. The screen layout is controlled by an active screen format that specifies which data streams are to be received, where on the screen to present the images and how to present the images. Type-independent data formatting is accomplished by choosing the preprocessing handler/transformation handler pair suitable for the type of a data stream and activating the handlers so that they restore images from the data stream and transform them to fit on the preallocated portion of the screen on the fly.

Abstract: A computer program version update system reduces storage space usage and enables calling programs to invoke any version of a program using the same name by storing only modified modules of a program for different program versions. Multiple versions of a program can thus have the same name. Any version of the program may be constructed from the modules upon command with a user issuing such a command and including a version number corresponding to the requested version as a parameter to invoke a program construction procedure.

Abstract: A system is provided to increase the efficiency of a VLIW, Very Long Insttion Word, processor which matches its level of parallelism, LOP, to the LOP of the executable code before executing the code's fixed-length VLIW instructions, so that object-level code compatibility is kept for different processor implementations of the same VLIW architecture required for different applications. Matching is accomplished either by reducing the LOP of the processor via inactivating the processor's functional units, or by effectively reducing the LOP of the executable code via the processor executing the sequential portions of each VLIW instruction in the code, with the length of the portions equal to or less than the number of operations that the processor can handle as a VLIW instruction.

Abstract: A memory access system using a machine instruction architecture having separate machine instructions to instruct a start of the atomic memory access and an end of the atomic memory access, respectively, comprises an atomic memory access memory array for storing a start/end of the atomic memory access, object memory region indicative information of an access request and an identifier of a subject of the access request, a means for generating combinatory signals thereof, a means for detecting the fact that a memory access request with discrepant identifiers has been newly issued for the object memory region to which the atomic memory access is being effected at present and a means for starting a processing routine corresponding thereto.

Abstract: A memory access system using a machine instruction architecture having separate machine instructions to instruct a start of the atomic memory access and an end of the atomic memory access, respectively, comprises an atomic memory access memory array for storing a start/end of the atomic memory access, an object memory region indicative of information of an access request and an identifier of a subject of the access request. The system can detect the fact that a memory access request with discrepant identifiers has been newly issued for the object memory region to which the atomic memory access is being effected at present and can immediately initiate a processing routine corresponding thereto. The system may also record a memory access history of the new memory request, whether or not the new memory access has been granted, and can continue or suspend an exclusive memory access request currently being executed.

Abstract: To eliminate the duplication of the same type of compilers, promote the effective use of a disk memory, and save user time and labor using a server machine under distributed environment where a plurality of different types of computers are interconnected by a network, a compiler-installed machine table showing the relationship between compilers for each type of machine and each language and machines holding the compilers, and a library-installed machine table showing the relationship between libraries for each type of machine and machines holding the libraries are provided in a server machine which operates on a specific machine. When the server machine receives a compile request from a client machine which operates on a machine under the above-mentioned environment, the machine searches for machines holding a compiler and libraries required for compilation requested by the client machine using these two tables, and transmits information on the machines to the client machine.

Abstract: A data processing system for array computation including a global memory, a control processor unit for executing microprograms preloaded from the global memory in a local memory of the processor unit, and an array processor unit controlled by the instructions generated by the control processor unit from the microprograms for executing array computations with an array of data preloaded from the global memory into a local array memory, the selected architecture of the array processor unit being dynamically reconfigurable to best meet array computation to be performed, and to provide reduced overhead operations.