Abstract: Provided is a storage subsystem capable of improving the data processing speed by balancing the load on processors and controllers. This storage subsystem includes a controller for controlling the input and output of data to and from a storage apparatus that provides to a host computer a plurality of logical units to become a storage extent for the host computer to read and write data, processes a command issued by the host computer, and has a storage resource in relation to the logical unit. The controller has a local memory for storing the command, and a processor configured from a plurality of cores for controlling the input and output of data to and from the logical unit to be subject to the input and output of the data based on the command. The local memory stores association information representing the correspondence between the plurality of logical units and the plurality of cores.

Abstract: Proposed is a storage controller and its control method for speeding up the processing time in response to a command in a simple manner while reducing the load of a controller that received a command targeting a non-associated logical volume. This storage controller includes a plurality of controllers for controlling the input and output of data to and from a corresponding logical unit based on a command retained in a local memory, and the local memory stores association information representing the correspondence of the logical units and the controllers and address information of the local memory in each of the controllers of a self-system and another-system.

Abstract: Provided is a storage subsystem capable of improving the data processing speed by balancing the load on processors and controllers. This storage subsystem includes a controller for controlling the input and output of data to and from a storage apparatus that provides to a host computer a plurality of logical units to become a storage extent for the host computer to read and write data, processes a command issued by the host computer, and has a storage resource in relation to the logical unit. The controller has a local memory for storing the command, and a processor configured from a plurality of cores for controlling the input and output of data to and from the logical unit to be subject to the input and output of the data based on the command. The local memory stores association information representing the correspondence between the plurality of logical units and the plurality of cores.

Abstract: Provided is a storage subsystem capable of improving the data processing speed by balancing the load on processors and controllers. This storage subsystem includes a controller for controlling the input and output of data to and from a storage apparatus that provides to a host computer a plurality of logical units to become a storage extent for the host computer to read and write data, processes a command issued by the host computer, and has a storage resource in relation to the logical unit. The controller has a local memory for storing the command, and a processor configured from a plurality of cores for controlling the input and output of data to and from the logical unit to be subject to the input and output of the data based on the command. The local memory stores association information representing the correspondence between the plurality of logical units and the plurality of cores.

Abstract: Provided is an information processing apparatus including a local memory for storing a control program, a flash memory for storing a boot program, a processor for controlling the overall controller, a chipset for relaying the transfer of data among the respective components, and a logical control circuit arranged between the chipset and the flash memory. The logical control circuit performs information conversion processing to accommodate the logical configuration of the chipset and the flash memory when sending and receiving information between the chipset and the flash memory. This information conversion processing includes the steps of translating a serial address signal output from the chipset into a parallel address signal, translating a serial data signal output from the chipset into a parallel data signal, and translating a parallel data signal output from the flash memory into a serial data signal.

Abstract: Provided is a storage subsystem capable of improving the data processing speed by balancing the load on processors and controllers. This storage subsystem includes a controller for controlling the input and output of data to and from a storage apparatus that provides to a host computer a plurality of logical units to become a storage extent for the host computer to read and write data, processes a command issued by the host computer, and has a storage resource in relation to the logical unit. The controller has a local memory for storing the command, and a processor configured from a plurality of cores for controlling the input and output of data to and from the logical unit to be subject to the input and output of the data based on the command. The local memory stores association information representing the correspondence between the plurality of logical units and the plurality of cores.

Abstract: Proposed is a storage controller and its control method for speeding up the processing time in response to a command in a simple manner while reducing the load of a controller that received a command targeting a non-associated logical volume. This storage controller includes a plurality of controllers for controlling the input and output of data to and from a corresponding logical unit based on a command retained in a local memory, and the local memory stores association information representing the correspondence of the logical units and the controllers and address information of the local memory in each of the controllers of a self-system and another-system.