Patents by Inventor Takahide Tanaka

Takahide Tanaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200177180
    Abstract: A semiconductor integrated circuit includes a level shifter formed in a portion of a high-voltage junction termination structure and an isolation region formed surrounding the periphery of the level shifter. The level shifter includes a p-type base region formed in an upper portion of a p? substrate, an n? source region formed contacting the base region, an n? drift region formed contacting the base region, a drain region formed in an upper portion of the drift region, and a control electrode that controls the voltage of the base region. In a planar pattern, an effective channel width defined by the width of the base region in a portion that overlaps with the control electrode is greater than the width of the drain region as measured along the same direction as the effective channel width.
    Type: Application
    Filed: November 4, 2019
    Publication date: June 4, 2020
    Applicant: Fuji Electric Co., Ltd.
    Inventor: Takahide TANAKA
  • Publication number: 20200093253
    Abstract: An electric toothbrush includes a gyro sensor inside a main body. The gyro sensor detects an angular velocity of the main body and the main body includes a head portion, a neck portion, and a grip portion in a longitudinal axis direction. An angle formed by a longitudinal axis of the main body in a state that brush bristles of the head portion contact with a brushing site in a dentition with respect to the longitudinal axis of the main body in a state that the brush bristles of the head portion contact with a reference position in the dentition is obtained, based on an output from the gyro sensor. A corresponding point corresponding to the brushing site on an approximate curve that curves corresponding to the dentition is obtained based on the angle, and coordinates of the corresponding point are used as a translational position of the brushing site.
    Type: Application
    Filed: November 25, 2019
    Publication date: March 26, 2020
    Applicant: OMRON HEALTHCARE Co., Ltd.
    Inventors: Hideaki YOSHIDA, Motofumi NAKANISHI, Tatsuya KOBAYASHI, Takahide TANAKA
  • Publication number: 20190387978
    Abstract: A height correction device measures height information on the reference position of the heart and height information on the wrist to which a blood pressure measurement device is attached using communication technology when the body of a subject rotates or moves at the position where the measurement device is attached during the measurement period including the sleep period, subjects the obtained blood pressure measurement values to height correction using height information, and approximates the obtained blood pressure measurement values to blood pressure measurement values measured at the reference position of the heart, to thereby obtain highly accurate measurement values.
    Type: Application
    Filed: August 28, 2019
    Publication date: December 26, 2019
    Inventors: Yumi KITAMURA, Takahide TANAKA, Shingo YAMASHITA
  • Patent number: 10508958
    Abstract: The potential difference between a piezo-resistive portion and a shield film is to be reduced. A semiconductor device is provided, including: a semiconductor substrate having provided therein a hollowed portion, a piezo-resistive portion provided in a region of the semiconductor substrate above the hollowed portion; an insulating film provided above the piezo-resistive portion; and a conductive shield film provided above the piezo-resistive portion with the insulating film intervening therebetween, wherein two different parts of the shield film are connected to different potentials. In this manner, the potential difference between a piezo-resistive portion and a shield film can be reduced.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: December 17, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Takahide Tanaka
  • Publication number: 20190352699
    Abstract: The present invention is directed to provide new PCR measuring method and device. As one embodiment of the present invention, a DNA detection method for detecting DNA in a droplet being present in oil, the droplet containing the DNA and a fluorescent labeled probe, the fluorescent labeled probe being hybridized to the DNA, the method including: a first step of amplifying the DNA in the the droplet by a nucleic acid amplification reaction; and a second step of measuring a melting temperature of the fluorescent labeled probe and the DNA in the droplet is provided.
    Type: Application
    Filed: November 16, 2017
    Publication date: November 21, 2019
    Inventors: Junko TANAKA, Takahide YOKOI, Masao KAMAHORI, Yoshinobu KOHARA
  • Patent number: 10458086
    Abstract: Described herein is a floating flap gate including a gate leaf having a buoyancy forming portion, the gate leaf being configured to be raised due to buoyancy effect (e.g., from water), a bottom fitting mounted to a proximal end portion of the gate leaf, the bottom fitting having a convex circular arc-shaped surface across a width direction of the gate leaf, a plate member having a concave circular arc-shaped surface to be mated with the convex circular arc-shaped surface of the bottom fitting when the gate leaf is in a lowered state, wherein the concave circular arc-shaped surface is in contact with the convex circular arc-shaped surface when the gate leaf is raised.
    Type: Grant
    Filed: August 19, 2015
    Date of Patent: October 29, 2019
    Assignee: HITACHI ZOSEN CORPORATION
    Inventors: Toshiaki Morii, Toshikazu Tanaka, Takahide Inagaki, Kyoichi Nakayasu
  • Patent number: 10396167
    Abstract: A resistive field plate including a spiral resistive element and meander resistive element is provided in an edge termination structure portion. The spiral resistive element is formed in a spiral planar layout, surrounding the periphery of a high-potential-side region to span from the high-potential-side region to a low-potential-side region. A spiral wire of the spiral resistive element includes a conductive film layer and a thin-film resistive layer connected to each other. The meander resistive element has ends positioned in the high-potential-side region and the low-potential-side region, and is provided in a meandering planar layout. The meander resistive element is provided at a same level as that of the thin-film resistive layer, and faces in the depth direction the conductive film layer of the spiral resistive element, sandwiching an interlayer insulating film therebetween. The conductive film layer of the spiral resistive element and the meander resistive element constitute a field plate.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: August 27, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takahide Tanaka, Masaharu Yamaji
  • Patent number: 10367056
    Abstract: An HVJT is includes a parasitic diode formed by pn junction between an n?-type diffusion region and a second p?-type separation region surrounding a periphery thereof. The n?-type diffusion region is arranged between an n-type diffusion region that is a high potential side region and an n-type diffusion region that is a low potential side region, and electrically separates these regions. In the n?-type diffusion region, an nchMOSFET of a level-up level shift circuit is arranged. The n?-type diffusion region has a planar layout in which the n?-type diffusion region surrounds a periphery of the n-type diffusion region and a region where the nchMOSFET is arranged protrudes inwardly. A high-concentration inter-region distance L1 of the nchMOS region where the nchMOSFET is arranged is longer than a high-concentration inter-region distance L2 of the parasitic diode. Thus, the reliability of the semiconductor device may be improved.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: July 30, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takahide Tanaka, Masaharu Yamaji
  • Publication number: 20190189610
    Abstract: A semiconductor integrated circuit includes: a p?-type semiconductor substrate defining a high-potential side circuit area and a low-potential side circuit area separated from each other; a high-side n well provided in an upper part of the semiconductor substrate in the high-potential side circuit area; a high-side p well provided in the high-side n well; and a p-type semiconductor region provided in an upper part of the semiconductor substrate in the low-potential side circuit area; and n+-type semiconductor region provided to be brought contact with the p-type semiconductor region, wherein a whole n-type semiconductor region including the n+-type semiconductor region, has an impurity concentration higher than an impurity concentration of the high-side n well.
    Type: Application
    Filed: October 25, 2018
    Publication date: June 20, 2019
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Takahide TANAKA
  • Patent number: 10249623
    Abstract: A semiconductor integrated circuit includes semiconductor substrate having a plurality of first potential side areas, including a first two adjacent first potential side areas, each first potential side area having a high potential side circuit, a first semiconductor region of a first conductivity type selectively provided in a surface layer on a front surface of a semiconductor substrate, a second semiconductor region of a second conductivity type selectively provided in the first semiconductor region, penetrating the first semiconductor region in a depth direction, a third semiconductor region of the first conductivity type selectively provided in the first semiconductor region so as to be separated from the second semiconductor region. Each of the first two adjacent first potential side areas includes a first side area facing the other, each first side area includes the third semiconductor region, and is free of the second semiconductor region.
    Type: Grant
    Filed: February 1, 2018
    Date of Patent: April 2, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Takahide Tanaka
  • Publication number: 20180269208
    Abstract: A semiconductor integrated circuit includes semiconductor substrate having a plurality of first potential side areas, including a first two adjacent first potential side areas, each first potential side area having a high potential side circuit, a first semiconductor region of a first conductivity type selectively provided in a surface layer on a front surface of a semiconductor substrate, a second semiconductor region of a second conductivity type selectively provided in the first semiconductor region, penetrating the first semiconductor region in a depth direction, a third semiconductor region of the first conductivity type selectively provided in the first semiconductor region so as to be separated from the second semiconductor region. Each of the first two adjacent first potential side areas includes a first side area facing the other, each first side area includes the third semiconductor region, and is free of the second semiconductor region.
    Type: Application
    Filed: February 1, 2018
    Publication date: September 20, 2018
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Takahide TANAKA
  • Publication number: 20180266901
    Abstract: The potential difference between a piezo-resistive portion and a shield film is to be reduced. A semiconductor device is provided, including: a semiconductor substrate having provided therein a hollowed portion, a piezo-resistive portion provided in a region of the semiconductor substrate above the hollowed portion; an insulating film provided above the piezo-resistive portion; and a conductive shield film provided above the piezo-resistive portion with the insulating film intervening therebetween, wherein two different parts of the shield film are connected to different potentials. In this manner, the potential difference between a piezo-resistive portion and a shield film can be reduced.
    Type: Application
    Filed: February 28, 2018
    Publication date: September 20, 2018
    Inventor: Takahide TANAKA
  • Patent number: 10043872
    Abstract: A semiconductor device includes a resistive element wherein a diffusion resistance region provided in an upper portion of a semiconductor base and a thin film resistance layer isolated and distanced from the semiconductor base and diffusion resistance region across an insulating film are alternately connected in series and alternately disposed in parallel.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: August 7, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takahide Tanaka, Masaharu Yamaji
  • Publication number: 20180069076
    Abstract: An HVJT is includes a parasitic diode formed by pn junction between an n?-type diffusion region and a second p?-type separation region surrounding a periphery thereof. The n?-type diffusion region is arranged between an n-type diffusion region that is a high potential side region and an n-type diffusion region that is a low potential side region, and electrically separates these regions. In the n?-type diffusion region, an nchMOSFET of a level-up level shift circuit is arranged. The n?-type diffusion region has a planar layout in which the n?-type diffusion region surrounds a periphery of the n-type diffusion region and a region where the nchMOSFET is arranged protrudes inwardly. A high-concentration inter-region distance L1 of the nchMOS region where the nchMOSFET is arranged is longer than a high-concentration inter-region distance L2 of the parasitic diode. Thus, the reliability of the semiconductor device may be improved.
    Type: Application
    Filed: October 31, 2017
    Publication date: March 8, 2018
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Takahide TANAKA, Masaharu YAMAJI
  • Patent number: 9773878
    Abstract: A semiconductor device includes a first main electrode terminal and second main electrode terminal disposed on the principal surface of a semiconductor substrate so as to be spaced from one another, an insulating film formed on the principal surface of the semiconductor substrate, and a thin film resistance layer. One end side of the thin film resistance layer is connected to the first main electrode terminal and the other end side of the thin film resistance layer is connected to the second main electrode terminal, the thin film resistance layer being spirally formed on the insulating film in such a way as to surround the first main electrode terminal. The thin film resistance layer extends while oscillating in a thickness direction of the semiconductor substrate.
    Type: Grant
    Filed: July 7, 2015
    Date of Patent: September 26, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takahide Tanaka, Masaharu Yamaji
  • Patent number: 9762048
    Abstract: A first sense resistor is connected between a fourth terminal of a power source potential of a high-potential region and a first terminal of a ground potential. A second sense resistor is connected between a third terminal of a reference potential of the high-potential region and the first terminal. A comparator is disposed in a low-potential region and uses the ground potential as a reference potential for operation. The comparator compares a voltage between an intermediate potential point of the first sense resistor and an intermediate potential point of the second sense resistor with a predetermined reference voltage. The output of the comparator is input through a control circuit and a level shift circuit to a high-side drive circuit driving an upper-arm IGBT. The output of the comparator is input to a driver circuit driving a lower-arm IGBT.
    Type: Grant
    Filed: November 1, 2016
    Date of Patent: September 12, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takahide Tanaka, Masaharu Yamaji
  • Publication number: 20170170647
    Abstract: A first sense resistor is connected between a fourth terminal of a power source potential of a high-potential region and a first terminal of a ground potential. A second sense resistor is connected between a third terminal of a reference potential of the high-potential region and the first terminal. A comparator is disposed in a low-potential region and uses the ground potential as a reference potential for operation. The comparator compares a voltage between an intermediate potential point of the first sense resistor and an intermediate potential point of the second sense resistor with a predetermined reference voltage. The output of the comparator is input through a control circuit and a level shift circuit to a high-side drive circuit driving an upper-arm IGBT. The output of the comparator is input to a driver circuit driving a lower-arm IGBT.
    Type: Application
    Filed: November 1, 2016
    Publication date: June 15, 2017
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Takahide TANAKA, Masaharu YAMAJI
  • Publication number: 20170170285
    Abstract: A resistive field plate including a spiral resistive element and meander resistive element is provided in an edge termination structure portion. The spiral resistive element is formed in a spiral planar layout, surrounding the periphery of a high-potential-side region to span from the high-potential-side region to a low-potential-side region. A spiral wire of the spiral resistive element includes a conductive film layer and a thin-film resistive layer connected to each other. The meander resistive element has ends positioned in the high-potential-side region and the low-potential-side region, and is provided in a meandering planar layout. The meander resistive element is provided at a same level as that of the thin-film resistive layer, and faces in the depth direction the conductive film layer of the spiral resistive element, sandwiching an interlayer insulating film therebetween. The conductive film layer of the spiral resistive element and the meander resistive element constitute a field plate.
    Type: Application
    Filed: December 12, 2016
    Publication date: June 15, 2017
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Takahide TANAKA, Masaharu YAMAJI
  • Publication number: 20160300912
    Abstract: A semiconductor device includes a resistive element wherein a diffusion resistance region provided in an upper portion of a semiconductor base and a thin film resistance layer isolated and distanced from the semiconductor base and diffusion resistance region across an insulating film are alternately connected in series and alternately disposed in parallel.
    Type: Application
    Filed: March 9, 2016
    Publication date: October 13, 2016
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Takahide TANAKA, Masaharu YAMAJI
  • Publication number: 20160056248
    Abstract: A semiconductor device includes a first main electrode terminal and second main electrode terminal disposed on the principal surface of a semiconductor substrate so as to be spaced from one another, an insulating film formed on the principal surface of the semiconductor substrate, and a thin film resistance layer. One end side of the thin film resistance layer is connected to the first main electrode terminal and the other end side of the thin film resistance layer is connected to the second main electrode terminal, the thin film resistance layer being spirally formed on the insulating film in such a way as to surround the first main electrode terminal. The thin film resistance layer extends while oscillating in a thickness direction of the semiconductor substrate.
    Type: Application
    Filed: July 7, 2015
    Publication date: February 25, 2016
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Takahide TANAKA, Masaharu YAMAJI