Patents by Inventor Takahide Tanaka
Takahide Tanaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240421197Abstract: A semiconductor device includes: a base body of a first conductivity-type; a first well region of a second conductivity-type provided in the base body and including a high-side circuit; a first voltage blocking region of the second conductivity-type provided along a circumference of the first well region; a second voltage blocking region of the first conductivity-type provided on an outer circumferential side of the first voltage blocking region; a first level shift element provided to encompass a part of the first voltage blocking region; a first isolation region of the first conductivity-type provided to surround a circumference of the first level shift element; and a field plate provided over the first voltage blocking region and the first isolation region with an insulating film interposed, the field plate having a first distance from the first isolation region greater than a second distance from the first voltage blocking region.Type: ApplicationFiled: April 22, 2024Publication date: December 19, 2024Applicant: FUJI ELECTRIC CO., LTD.Inventor: Takahide TANAKA
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Publication number: 20240268766Abstract: A blood-pressure-measuring device includes: a feature amount acquisition unit that acquires one or more feature amounts related to estimation of a blood pressure value of a human body; a blood pressure value calculation unit that calculates an estimated blood pressure value based on the feature amount; an actually measured blood pressure value acquisition unit that acquires an actually measured blood pressure value measured by a method different from the calculation by the blood pressure value calculation unit; a calibration determination unit that determines whether or not the feature amount acquired by the feature amount acquisition unit deviates from a predetermined reference value, the calibration determination unit determining to acquire the actually measured blood pressure value when the calibration determination unit has determined that the feature amount deviates; and a calibration processing unit that estimates blood pressure value.Type: ApplicationFiled: February 15, 2024Publication date: August 15, 2024Inventors: Yasuhiro KAWABATA, Kenji FUJII, Naomi MATSUMURA, Akito ITO, Yuki SAKAGUCHI, Takahide TANAKA
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Publication number: 20240258309Abstract: A semiconductor device includes: a substrate body of a first conductivity-type; a first well region of a second conductivity-type provided in the substrate body and provided with a high-side circuit; a first voltage blocking region of the second conductivity-type provided around the first well region; a contact region of the second conductivity-type provided at an upper part of the first well region or the first voltage blocking region; a second voltage blocking region of the first conductivity-type provided on an outer circumferential side of the first voltage blocking region so as to be in contact with the first voltage blocking region; a first isolation region of the first conductivity-type provided to electrically isolate, from the first well region, an opposed part of the first voltage blocking region opposed to a low-side circuit provided on an outer circumferential side of the second voltage blocking region; and a level shifter.Type: ApplicationFiled: November 27, 2023Publication date: August 1, 2024Applicant: FUJI ELECTRIC CO., LTD.Inventor: Takahide TANAKA
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Publication number: 20230178540Abstract: A semiconductor device includes: a first conductivity type base body; a second conductivity type well region provided on the base body and formed with a high potential side circuit; a second conductivity type voltage blocking area provided to surround a periphery of the well region; a level shifter having a second conductivity type drift region provided on the base body, a second conductivity type carrier reception region provided in an upper part of the drift region, a first conductivity type base region provided in contact with the drift region, a first gate electrode provided on the base region, and a second conductivity type carrier supply region provided in an upper part of the base region; a first conductivity type isolation region provided between the voltage blocking area and the drift region on the base body; and a second gate electrode on the isolation region.Type: ApplicationFiled: October 27, 2022Publication date: June 8, 2023Applicant: FUJI ELECTRIC CO., LTD.Inventor: Takahide TANAKA
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Patent number: 11484113Abstract: An electric toothbrush includes a gyro sensor inside a main body. The gyro sensor detects an angular velocity of the main body and the main body includes a head portion, a neck portion, and a grip portion in a longitudinal axis direction. An angle formed by a longitudinal axis of the main body in a state that brush bristles of the head portion contact with a brushing site in a dentition with respect to the longitudinal axis of the main body in a state that the brush bristles of the head portion contact with a reference position in the dentition is obtained, based on an output from the gyro sensor. A corresponding point corresponding to the brushing site on an approximate curve that curves corresponding to the dentition is obtained based on the angle, and coordinates of the corresponding point are used as a translational position of the brushing site.Type: GrantFiled: November 25, 2019Date of Patent: November 1, 2022Assignee: OMRON HEALTHCARE Co., Ltd.Inventors: Hideaki Yoshida, Motofumi Nakanishi, Tatsuya Kobayashi, Takahide Tanaka
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Patent number: 11330992Abstract: A height correction device measures height information on the reference position of the heart and height information on the wrist to which a blood pressure measurement device is attached using communication technology when the body of a subject rotates or moves at the position where the measurement device is attached during the measurement period including the sleep period, subjects the obtained blood pressure measurement values to height correction using height information, and approximates the obtained blood pressure measurement values to blood pressure measurement values measured at the reference position of the heart, to thereby obtain highly accurate measurement values.Type: GrantFiled: August 28, 2019Date of Patent: May 17, 2022Assignees: OMRON CORPORATION, OMRON HEALTHCARE CO., LTD.Inventors: Yumi Kitamura, Takahide Tanaka, Shingo Yamashita
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Patent number: 11257806Abstract: A semiconductor integrated circuit includes: a p?-type semiconductor substrate defining a high-potential side circuit area and a low-potential side circuit area separated from each other; a high-side n well provided in an upper part of the semiconductor substrate in the high-potential side circuit area; a high-side p well provided in the high-side n well; and a p-type semiconductor region provided in an upper part of the semiconductor substrate in the low-potential side circuit area; and n+-type semiconductor region provided to be brought contact with the p-type semiconductor region, wherein a whole n-type semiconductor region including the n+-type semiconductor region, has an impurity concentration higher than an impurity concentration of the high-side n well.Type: GrantFiled: August 6, 2020Date of Patent: February 22, 2022Assignee: FUJI ELECTRIC CO., LTD.Inventor: Takahide Tanaka
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Publication number: 20200365577Abstract: A semiconductor integrated circuit includes: a p?-type semiconductor substrate defining a high-potential side circuit area and a low-potential side circuit area separated from each other; a high-side n well provided in an upper part of the semiconductor substrate in the high-potential side circuit area; a high-side p well provided in the high-side n well; and a p-type semiconductor region provided in an upper part of the semiconductor substrate in the low-potential side circuit area; and n+-type semiconductor region provided to be brought contact with the p-type semiconductor region, wherein a whole n-type semiconductor region including the n+-type semiconductor region, has an impurity concentration higher than an impurity concentration of the high-side n well.Type: ApplicationFiled: August 6, 2020Publication date: November 19, 2020Applicant: FUJI ELECTRIC CO., LTD.Inventor: Takahide TANAKA
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Patent number: 10770450Abstract: A semiconductor integrated circuit includes: a p?-type semiconductor substrate defining a high-potential side circuit area and a low-potential side circuit area separated from each other; a high-side n well provided in an upper part of the semiconductor substrate in the high-potential side circuit area; a high-side p well provided in the high-side n well; and a p-type semiconductor region provided in an upper part of the semiconductor substrate in the low-potential side circuit area; and n+-type semiconductor region provided to be brought contact with the p-type semiconductor region, wherein a whole n-type semiconductor region including the n+-type semiconductor region, has an impurity concentration higher than an impurity concentration of the high-side n well.Type: GrantFiled: October 25, 2018Date of Patent: September 8, 2020Assignee: FUJI ELECTRIC CO., LTD.Inventor: Takahide Tanaka
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Patent number: 10763854Abstract: A semiconductor integrated circuit includes a level shifter formed in a portion of a high-voltage junction termination structure and an isolation region formed surrounding the periphery of the level shifter. The level shifter includes a p-type base region formed in an upper portion of a p? substrate, an n? source region formed contacting the base region, an n+ drift region formed contacting the base region, a drain region formed in an upper portion of the drift region, and a control electrode that controls the voltage of the base region. In a planar pattern, an effective channel width defined by the width of the base region in a portion that overlaps with the control electrode is greater than the width of the drain region as measured along the same direction as the effective channel width.Type: GrantFiled: November 4, 2019Date of Patent: September 1, 2020Assignee: FUJI ELECTRIC CO., LTD.Inventor: Takahide Tanaka
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Publication number: 20200177180Abstract: A semiconductor integrated circuit includes a level shifter formed in a portion of a high-voltage junction termination structure and an isolation region formed surrounding the periphery of the level shifter. The level shifter includes a p-type base region formed in an upper portion of a p? substrate, an n? source region formed contacting the base region, an n? drift region formed contacting the base region, a drain region formed in an upper portion of the drift region, and a control electrode that controls the voltage of the base region. In a planar pattern, an effective channel width defined by the width of the base region in a portion that overlaps with the control electrode is greater than the width of the drain region as measured along the same direction as the effective channel width.Type: ApplicationFiled: November 4, 2019Publication date: June 4, 2020Applicant: Fuji Electric Co., Ltd.Inventor: Takahide TANAKA
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Publication number: 20200093253Abstract: An electric toothbrush includes a gyro sensor inside a main body. The gyro sensor detects an angular velocity of the main body and the main body includes a head portion, a neck portion, and a grip portion in a longitudinal axis direction. An angle formed by a longitudinal axis of the main body in a state that brush bristles of the head portion contact with a brushing site in a dentition with respect to the longitudinal axis of the main body in a state that the brush bristles of the head portion contact with a reference position in the dentition is obtained, based on an output from the gyro sensor. A corresponding point corresponding to the brushing site on an approximate curve that curves corresponding to the dentition is obtained based on the angle, and coordinates of the corresponding point are used as a translational position of the brushing site.Type: ApplicationFiled: November 25, 2019Publication date: March 26, 2020Applicant: OMRON HEALTHCARE Co., Ltd.Inventors: Hideaki YOSHIDA, Motofumi NAKANISHI, Tatsuya KOBAYASHI, Takahide TANAKA
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Publication number: 20190387978Abstract: A height correction device measures height information on the reference position of the heart and height information on the wrist to which a blood pressure measurement device is attached using communication technology when the body of a subject rotates or moves at the position where the measurement device is attached during the measurement period including the sleep period, subjects the obtained blood pressure measurement values to height correction using height information, and approximates the obtained blood pressure measurement values to blood pressure measurement values measured at the reference position of the heart, to thereby obtain highly accurate measurement values.Type: ApplicationFiled: August 28, 2019Publication date: December 26, 2019Inventors: Yumi KITAMURA, Takahide TANAKA, Shingo YAMASHITA
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Patent number: 10508958Abstract: The potential difference between a piezo-resistive portion and a shield film is to be reduced. A semiconductor device is provided, including: a semiconductor substrate having provided therein a hollowed portion, a piezo-resistive portion provided in a region of the semiconductor substrate above the hollowed portion; an insulating film provided above the piezo-resistive portion; and a conductive shield film provided above the piezo-resistive portion with the insulating film intervening therebetween, wherein two different parts of the shield film are connected to different potentials. In this manner, the potential difference between a piezo-resistive portion and a shield film can be reduced.Type: GrantFiled: February 28, 2018Date of Patent: December 17, 2019Assignee: FUJI ELECTRIC CO., LTD.Inventor: Takahide Tanaka
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Patent number: 10396167Abstract: A resistive field plate including a spiral resistive element and meander resistive element is provided in an edge termination structure portion. The spiral resistive element is formed in a spiral planar layout, surrounding the periphery of a high-potential-side region to span from the high-potential-side region to a low-potential-side region. A spiral wire of the spiral resistive element includes a conductive film layer and a thin-film resistive layer connected to each other. The meander resistive element has ends positioned in the high-potential-side region and the low-potential-side region, and is provided in a meandering planar layout. The meander resistive element is provided at a same level as that of the thin-film resistive layer, and faces in the depth direction the conductive film layer of the spiral resistive element, sandwiching an interlayer insulating film therebetween. The conductive film layer of the spiral resistive element and the meander resistive element constitute a field plate.Type: GrantFiled: December 12, 2016Date of Patent: August 27, 2019Assignee: FUJI ELECTRIC CO., LTD.Inventors: Takahide Tanaka, Masaharu Yamaji
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Patent number: 10367056Abstract: An HVJT is includes a parasitic diode formed by pn junction between an n?-type diffusion region and a second p?-type separation region surrounding a periphery thereof. The n?-type diffusion region is arranged between an n-type diffusion region that is a high potential side region and an n-type diffusion region that is a low potential side region, and electrically separates these regions. In the n?-type diffusion region, an nchMOSFET of a level-up level shift circuit is arranged. The n?-type diffusion region has a planar layout in which the n?-type diffusion region surrounds a periphery of the n-type diffusion region and a region where the nchMOSFET is arranged protrudes inwardly. A high-concentration inter-region distance L1 of the nchMOS region where the nchMOSFET is arranged is longer than a high-concentration inter-region distance L2 of the parasitic diode. Thus, the reliability of the semiconductor device may be improved.Type: GrantFiled: October 31, 2017Date of Patent: July 30, 2019Assignee: FUJI ELECTRIC CO., LTD.Inventors: Takahide Tanaka, Masaharu Yamaji
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Publication number: 20190189610Abstract: A semiconductor integrated circuit includes: a p?-type semiconductor substrate defining a high-potential side circuit area and a low-potential side circuit area separated from each other; a high-side n well provided in an upper part of the semiconductor substrate in the high-potential side circuit area; a high-side p well provided in the high-side n well; and a p-type semiconductor region provided in an upper part of the semiconductor substrate in the low-potential side circuit area; and n+-type semiconductor region provided to be brought contact with the p-type semiconductor region, wherein a whole n-type semiconductor region including the n+-type semiconductor region, has an impurity concentration higher than an impurity concentration of the high-side n well.Type: ApplicationFiled: October 25, 2018Publication date: June 20, 2019Applicant: FUJI ELECTRIC CO., LTD.Inventor: Takahide TANAKA
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Patent number: 10249623Abstract: A semiconductor integrated circuit includes semiconductor substrate having a plurality of first potential side areas, including a first two adjacent first potential side areas, each first potential side area having a high potential side circuit, a first semiconductor region of a first conductivity type selectively provided in a surface layer on a front surface of a semiconductor substrate, a second semiconductor region of a second conductivity type selectively provided in the first semiconductor region, penetrating the first semiconductor region in a depth direction, a third semiconductor region of the first conductivity type selectively provided in the first semiconductor region so as to be separated from the second semiconductor region. Each of the first two adjacent first potential side areas includes a first side area facing the other, each first side area includes the third semiconductor region, and is free of the second semiconductor region.Type: GrantFiled: February 1, 2018Date of Patent: April 2, 2019Assignee: FUJI ELECTRIC CO., LTD.Inventor: Takahide Tanaka
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Publication number: 20180269208Abstract: A semiconductor integrated circuit includes semiconductor substrate having a plurality of first potential side areas, including a first two adjacent first potential side areas, each first potential side area having a high potential side circuit, a first semiconductor region of a first conductivity type selectively provided in a surface layer on a front surface of a semiconductor substrate, a second semiconductor region of a second conductivity type selectively provided in the first semiconductor region, penetrating the first semiconductor region in a depth direction, a third semiconductor region of the first conductivity type selectively provided in the first semiconductor region so as to be separated from the second semiconductor region. Each of the first two adjacent first potential side areas includes a first side area facing the other, each first side area includes the third semiconductor region, and is free of the second semiconductor region.Type: ApplicationFiled: February 1, 2018Publication date: September 20, 2018Applicant: FUJI ELECTRIC CO., LTD.Inventor: Takahide TANAKA
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Publication number: 20180266901Abstract: The potential difference between a piezo-resistive portion and a shield film is to be reduced. A semiconductor device is provided, including: a semiconductor substrate having provided therein a hollowed portion, a piezo-resistive portion provided in a region of the semiconductor substrate above the hollowed portion; an insulating film provided above the piezo-resistive portion; and a conductive shield film provided above the piezo-resistive portion with the insulating film intervening therebetween, wherein two different parts of the shield film are connected to different potentials. In this manner, the potential difference between a piezo-resistive portion and a shield film can be reduced.Type: ApplicationFiled: February 28, 2018Publication date: September 20, 2018Inventor: Takahide TANAKA