Abstract: A semiconductor memory device has a memory region which is formed on a semiconductor substrate and in which a plurality of memory cells each including a memory transistor are arranged as a matrix using a plurality of impurity diffusion layers (bit lines) and a plurality of gate electrodes (word lines) intersecting each other. The gate electrode of each of the memory transistors has an upper surface thereof formed into a protruding portion which is higher in level at the middle portion than at the edge portions. A silicide layer is formed on the upper surface of the protruding portion of the gate electrode of each of the memory transistors.

Abstract: A semiconductor memory is provided with memory cells including bit lines made of a diffusion layer formed in a semiconductor substrate, charge-trapping gate insulating films formed between the bit lines and word lines formed on the gate insulating films. An interlayer insulating film is formed over the memory cells and bit line contact plugs are formed in the interlayer insulating film to be connected to the bit lines. Further, a light blocking film is formed on at least part of the interlayer insulating film covering the memory cells and part of the light blocking film formed on the interlayer insulating film extends from the surface to the inside of the interlayer insulating film in the neighborhood of the bit line contact plugs.

Abstract: A semiconductor memory is provided with memory cells including bit lines made of a diffusion layer formed in a semiconductor substrate, charge-trapping gate insulating films formed between the bit lines and word lines formed on the gate insulating films. An interlayer insulating film is formed over the memory cells and bit line contact plugs are formed in the interlayer insulating film to be connected to the bit lines. Further, a light blocking film is formed on at least part of the interlayer insulating film covering the memory cells and part of the light blocking film formed on the interlayer insulating film extends from the surface to the inside of the interlayer insulating film in the neighborhood of the bit line contact plugs.

Abstract: A semiconductor memory device has a memory region which is formed on a semiconductor substrate and in which a plurality of memory cells each including a memory transistor are arranged as a matrix using a plurality of impurity diffusion layers (bit lines) and a plurality of gate electrodes (word lines) intersecting each other. The gate electrode of each of the memory transistors has an upper surface thereof formed into a protruding portion which is higher in level at the middle portion than at the edge portions. A silicide layer is formed on the upper surface of the protruding portion of the gate electrode of each of the memory transistors.

Abstract: A gate structure composed of a tunnel insulation film, a floating gate electrode, a capacitive insulation film and a control gate electrode is formed on a semiconductor substrate. Then, ion injection adjustment films that are in contact with the floating gate electrode at least on the side surfaces of the floating gate electrode are formed. After injecting impurity ions into the active region beside the gate structure in the semiconductor substrate while using the gate structure and the ion injection adjustment film as masks, the injected impurity ions are diffused thermally by performing heat treatment on the active region. Film thickness of the ion injection adjustment film is selected to a value to prevent the impurity ions from being injected into the tunnel insulation film and allows the impurity ions to reach lower portions of side end of the floating gate electrode in the active region as a result of diffusive scattering of impurity ions in the semiconductor substrate.

Abstract: A silicon dioxide film, located over an active region in a well, is annealed at 1050° C. within an N2O ambient, thereby diffusing nitrogen into the silicon dioxide film and forming a nitrogen-containing silicon dioxide film. Next, two polysilicon films, interposing an ONO film therebetween, are deposited and then those films are patterned. In this manner, a memory gate electrode section, consisting of floating gate electrode, interelectrode insulating film and control gate electrode, is formed on the nitrogen-containing silicon dioxide film as a tunnel insulating film. At the same time, a select gate electrode section is also formed beside the memory gate electrode section. Then, p-type source/drain regions and intermediate diffused region are defined below these electrode sections. In this structure, electrons can be injected through a particular part of the tunnel insulating film and holes are trapped in a limited region of the tunnel insulating film.

Abstract: A circuit for testing a nonvolatile semiconductor memory includes a serial connection of flash memory cells as a first memory group. In the serial connection, the gates of the flash memory cells have been connected to each other, and a first one of the cells has its source or drain connected to the source or drain of a second one of the cells when the first and second cells are adjacent to each other.

Abstract: A gate structure composed of a tunnel insulation film, a floating gate electrode, a capacitive insulation film and a control gate electrode is formed on a semiconductor substrate. Then, ion injection adjustment films that are in contact with the floating gate electrode at least on the side surfaces of the floating gate electrode are formed. After injecting impurity ions into the active region beside the gate structure in the semiconductor substrate while using the gate structure and the ion injection adjustment film as masks, the injected impurity ions are diffused thermally by performing heat treatment on the active region. Film thickness of the ion injection adjustment film is selected to a value to prevent the impurity ions from being injected into the tunnel insulation film and allows the impurity ions to reach lower portions of side end of the floating gate electrode in the active region as a result of diffusive scattering of impurity ions in the semiconductor substrate.

Abstract: A circuit for testing a nonvolatile semiconductor memory includes a serial connection of flash memory cells as a first memory group. In the serial connection, the gates of the flash memory cells have been connected to each other, and a first one of the cells has its source or drain connected to the source or drain of a second one of the cells when the first and second cells are adjacent to each other.

Abstract: A silicon dioxide film, located over an active region in a well, is annealed at 1050° C. within an N2O ambient, thereby diffusing nitrogen into the silicon dioxide film and forming a nitrogen-containing silicon dioxide film. Next, two polysilicon films, interposing an ONO film therebetween, are deposited and then those films are patterned. In this manner, a memory gate electrode section, consisting of floating gate electrode, interelectrode insulating film and control gate electrode, is formed on the nitrogen-containing silicon dioxide film as a tunnel insulating film. At the same time, a select gate electrode section is also formed beside the memory gate electrode section. Then, p-type source/drain regions and intermediate diffused region are defined below these electrode sections. In this structure, electrons can be injected through a particular part of the tunnel insulating film and holes are trapped in a limited region of the tunnel insulating film.