Abstract: A decimation filter has: a plurality of calculating devices each having a multiplier and an accumulator; a plurality of coefficient memories (a ring memory and shift registers) which store filter coefficients, and which correspond to the calculating devices, respectively; and a selector which sequentially selectively outputs the outputs of the plurality of calculating devices in synchronization with a clock signal. When a decimation ratio is n, filter coefficients which are sequentially shifted by an n number of filter coefficients are read out from the plurality of coefficient memories, and multiplied with a signal in the multipliers of the calculating devices, and results of the multiplications are accumulated in the accumulators to be output.

Abstract: A decimation filter has: a plurality of calculating devices each having a multiplier and an accumulator; a plurality of coefficient memories (a ring memory and shift registers) which store filter coefficients, and which correspond to the calculating devices, respectively; and a selector which sequentially selectively outputs the outputs of the plurality of calculating devices in synchronization with a clock signal. When a decimation ratio is n, filter coefficients which are sequentially shifted by an n number of filter coefficients are read out from the plurality of coefficient memories, and multiplied with a signal in the multipliers of the calculating devices, and results of the multiplications are accumulated in the accumulators to be output.

Abstract: Volume adjustment is performed in small steps at a DSP (12) and volume adjustment is performed in wide steps at electronic volume circuits (18L, 18R). Adjustment only by the DSP (12) is performed for a small volume range less than or equal to a predetermined level. For a volume higher than or equal to the predetermined level, fine adjustment by the DSP (12) at the transient period of volume adjustment is combined to reduce the increment of variation so that the volume adjustment is performed gradually.

Abstract: A receiver receives FM multiplex broadcast data of both RDS and DARC systems by using one front end. A BIC detection circuit (101) detects a block identification code (BIC) included in received data. A coincidence/non-coincidence detection circuit (104) judges whether or not a BIC detection timing is correct and emits a coincidence/non-coincidence pulse. A forward protection circuit (106) counts a frequency of outputs of non-coincidence pulses and retains an established synchronous condition until the counted value exceeds a predetermined value. Then, a forward protection control circuit (108) inhibits the forward protection circuit from performing a count operation while a search is performed for selecting a station. Also, a rearward protection circuit (105) counts a frequency of outputs of coincidence pulses and establishes a synchronous condition when the counted value reaches a predetermined value.

Abstract: Volume adjustment is performed in small steps at a DSP (12) and volume adjustment is performed in wide steps at electronic volume circuits (18L, 18R). Adjustment only by the DSP (12) is performed for a small volume range less than or equal to a predetermined level. For a volume higher than or equal to the predetermined level, fine adjustment by the DSP (12) at the transient period of volume adjustment is combined to reduce the increment of variation so that the volume adjustment is performed gradually.

Abstract: Received signals are digitized by a comparator, and sampled by regenerated clock signals synchronized to a carrier. Biphase symbol data are demodulated based on the sampling data. A biphase decoder circuit performs subtraction of the biphase symbol data to be paired. The subtraction result is compared with threshold values by data judgment circuitry which then judges inversion of the biphase signals to be paired. An RDS-ID detector circuit detects inversion of RDS signals by detection of either continuity or a ratio of signals received for a certain length period. Alternatively, RDS signals are detected by stability of output from the pair judgment circuit to detect a combination of biphase symbols.

Abstract: An RDS signal is binarized by a comparator (2) and the output is sampled by a regeneration clock in synchronism with a regeneration carrier to provide sampled data. Then, by means of an accumulator (an adder 6 and a D-FF7) or a low pass filter (12), an integration result of the sampled output is obtained for each biphase symbol and by means of a biphase decoder circuit (9), the integration results are subjected to a subtraction between two symbols making up a pair. A differentially coded RDS data can be obtained using the sign of the subtraction result, which is differentially decoded in a differential decoder circuit (11) to provide an RDS data. In addition, the absolute value of the subtraction result is compared with a predetermined threshold value to provide reliability data for each differentially coded RDS data using the comparison result. The lower one of the consecutive reliability data may be assumed to be the reliability data for the RDS data.

Abstract: A demodulating circuit demodulates a received signal, and outputs patterns of demodulated data and reliability information bits indicating correctness of the demodulated data. These are supplied to first and second shift registers (4 and 5), respectively. When the number of reliability information bits of Level 1 in the second shift register is a predetermined value or less, a shift operation is repeated a plurality of times. When a reliability information bit of Level 1 is outputted, an error correction control circuit (7) successively outputs all possible bit patterns of the demodulated data An EXOR gate (10) generates all possible patterns of demodulated data An error correcting circuit (11) carries out error correction for all the patterns. When the number is larger than the predetermined value, the error correction is carried out only for the demodulated data supplied from the demodulating circuit in a conventional manner.

Abstract: Superimposed FM data is demodulated to digital data. A synchronism reproducing circuit (data block detecting section) detects the front of blocks in the digital data to generate a block head signal (a station change timing signal), which is supplied to a control section of a station selecting microcomputer. When a station selecting key requests a change of the received station, station data corresponding to a requested station is supplied to the control section (a station selecting control section). When the block head signal is inputted after requesting the change of the station, the control section begins to output station change data to a PLL frequency synthesizer in order to change the frequency signal in a front end. This prevents a latter part of a block in received superimposed FM data from being NG data.

Abstract: An offset circuit (2) detects an offset word serving as a synchronization pattern. By being triggered by the detection, main and subordinate synchronization detection circuits (5 and 6) detect the periodicity of the offset word only during a predetermined backward guard period. Both synchronization detection circuits (5 and 6) detect offset words at different timings. Therefore, if one synchronization detection circuit (5 or 6) fails in detection of synchronization, it is possible to use a detection result of the other synchronization detection circuit (5 or 6). Moreover, received data during the backward guard period is stored in a data memory (11). Therefore, it is possible to use the stored data as received data after detection of synchronization. Even after establishment of synchronization, the synchronization detection circuit (5 or 6) continuously detects the periodicity of an offset word at a timing different from an established timing.

Abstract: In accordance with the operation of an operating section 14, a control section 12 performs a reception control operation and demodulates a signal passing through a band pass filter 7 for extracting a multiplex signal using a multiplex signal demodulating section 8 when receiving a broadcast signal. A block synchronization circuit 16 of a synchronization circuit 9 carries out block synchronization processing on the demodulated signal. When block synchronization is established, a synchronization determination signal is supplied to a detecting section DET and the detecting section DET determines that a broadcasting station whose radio waves are currently being received is a multiplex broadcasting station.

Abstract: A digital modulating signal, which is a binary conversion of an RDS signal by a comparator, is sampled by a D-FF with a regeneration clock synchronized with a carrier regenerated by a carrier regeneration circuit. Next, a comparator output is input by an edge detection circuit where a data edge is detected, and the edge interval between this edge and the sampling timing edge of the regeneration clock is detected by a reliability judgment circuit where the edge interval is encoded and output as reliability data. Then, the reliability data is added as LSB data to various sampling data, and data for various symbols is regenerated at the data regeneration circuit. This minimizes the influence of the error data on the data regeneration circuit even if data is sampled erroneously.

Abstract: In multiplex FM broadcasting, a digital signal is composed of a frame which consists of a predetermined number of blocks in the vertical direction, a block consisting of a predetermined number of bits in the horizontal direction and having a horizontal parity (error correcting code) for correcting errors in the horizontal direction and a vertical parity for correcting errors in the vertical direction. The block also has a control bit for determining whether the error correction in the horizontal direction is to be carried out only once. A decoding identification detector (20) detects the content of the control bit, a controller (12) controls the re-writing of the digital signal into a frame buffer (13) after the error correction of the digital signal in the vertical direction by an error corrector (14).

Abstract: An SI judging circuit in a service detecting section detects a service identification code included in a block included in received superimposed FM data. When the block represents an unnecessary service, the SI judging circuit generates a predetermined service detecting signal, which is supplied to a station selecting microcomputer. A user operates a station selecting key to request the change of the broadcasting station. When the change is requested, and also the service detecting signal indicating that the service included in the received block is not needed is supplied to the station selecting microcomputer by the SI judging circuit, a control section of the station selecting microcomputer outputs station data corresponding to the requested station to a PLL synthesizer, and then the frequency signal (tuning frequency) is changed at a front end.

Abstract: Disclosed is a MUSE decoder for a pixel signal sampled in accordance with Multiple Sub-nyquist Sampling Encoding (MUSE). An interframe interpolation circuit (142) applies a pixel signal Sg which is not subjected to noise reduction processing to an intrafield interpolation circuit (18') for motion picture processing through a signal line (L5). A pixel signal delayed, which is outputted from delay circuits (24a, 24b) is subjected to a required noise reduction processing by an adder 60. Since the intrafield interpolation circuit 18' receives the pixel signal Sg which is not subjected to the noise reduction processing, an adverse influence on a motion picture, which may be caused by the noise reduction, is prevented even in case that the delay circuits (24a, 24b) are shared for motion picture processing and still picture processing.

Abstract: Disclosed is an intrafield interpolation circuit for interpolating pixel signals between pixel signals sampled based on Multiple Sub-nyquist Sampling Encoding (MUSE). There are provided in this interpolation circuit switches (S4a, S4b, S4c) for selecting pixel signals from delay elements (33h, 33i, 33j). Since these switches are controlled at a suitable timing, correct pixel signals obtained by an operation are interpolated between the sampled pixel signals. In addition, since pixel signals required only for an interpolation processing are handled, multipliers require half the operation speed of a conventional circuit, resulting in an enhanced reliability in operation.

Abstract: A time compressed color difference signal included in a high definition television signal is roughly compensated for its units of an interval of one-half of a transmission sampling interval in a range obtained by multiplying the amount of a horizontal motion vector by a compression rate. In addition, the time compressed color difference signal roughly compensated for its finely compensated for in a horizontal direction in units of an interval of one-half of the transmission sampling interval or less by a one-dimensional or two-demensional spacial filter. Futhermore, the time compressed color difference signal is compensaed for in a vertical direction by a distance corresponding to the amount of a vertical motion vector.