Patents by Inventor Takahiko Moriya
Takahiko Moriya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 5637153Abstract: After a polysilicon film is formed on a wafer, a cleaning gas containing ClF.sub.3 at 10 to 50 vol % is supplied into a reaction tube and an exhaust pipe system at a flow rate of 3000 to 3500 SCCM, so as to remove a polysilicon-based film deposited on an inner wall surface of the reaction tube, the surface of a member incorporated in the reaction tube, and an inner wall surface of the exhaust pipe system while the film forming process, by etching using ClF.sub.3. The cleaning gas is supplied while the temperature in the reaction tube is maintained at 450.degree. C. or higher, and in a pressure condition set at the maintained temperature such that an etching rate of the polysilicon-based film by the cleaning gas is higher than an etching rate of silicon which is the material of the reaction tube or the member incorporated in the reaction tube.Type: GrantFiled: April 26, 1995Date of Patent: June 10, 1997Assignee: Tokyo Electron LimitedInventors: Reiji Niino, Yoshiyuki Fujita, Hideki Lee, Yasuo Imamura, Toshiharu Nishimura, Yuuichi Mikata, Shinji Miyazaki, Takahiko Moriya, Katsuya Okumura, Hitoshi Kato
-
Patent number: 5580615Abstract: A method of forming a conductive film on an insulating region of a substrate wherein a surface of the insulating region formed on the substrate is activated by irradiating the surface with electrons, ions or light. Next, a metal film pattern constituting, for example, an electrical interconnection, is deposited on the surface by applying a selective chemical vapor deposition process using a metal halide gas.Type: GrantFiled: April 7, 1994Date of Patent: December 3, 1996Assignee: Kabushiki Kaisha ToshibaInventors: Hitoshi Itoh, Takahiko Moriya
-
Patent number: 5380370Abstract: Prior to formation of a polysilicon film on a wafer, a pre-coat film having a thickness of 1 .mu.m and consisting of polysilicon is formed on the inner wall surface of a reaction tube or the surface of a member incorporated in the reaction tube. A polysilicon film is formed on the wafer at a temperature of 450.degree. C. to 650.degree. C. A cleaning gas containing ClF.sub.3 having a concentration of 10 to 50 vol. % is supplied into the reaction tube at a flow rate to an area of an object be cleaned of 750 to 3,500 SCCM/m.sup.2 to remove a polysilicon film deposited on the inner wall surface of the reaction tube or the surface of the member incorporated in the reaction tube by etching using the ClF.sub.3. In this case, the cleaning gas is supplied while a temperature in the reaction tube is kept at a temperature of 450.degree. C. to 650.degree. C.Type: GrantFiled: April 30, 1993Date of Patent: January 10, 1995Assignee: Tokyo Electron LimitedInventors: Reiji Niino, Yoshiyuki Fujita, Hideki Lee, Yasuo Imamura, Toshiharu Nishimura, Yuuichi Mikata, Shinji Miyazaki, Takahiko Moriya, Katsuya Okumura
-
Patent number: 5252133Abstract: A vertically oriented CVD apparatus comprises a reaction chamber, a boat means vertically placed in the reaction chamber to horizontally support a plurality of semiconductor substrates, and a gas inlet tube including a plurality of gas injection holes along a longitudinal axis thereof and extending along a longitudinal side of the boat means to introduce a reaction gas into the reaction chamber. In the structure, a direction of each of the gas injection holes is set at an angle .theta. with respect to a reference line given by a straight line connecting a center of the gas inlet tube to a center of one of the semiconductor wafers, the angle .theta. being defined by 0.degree. < .theta. .ltoreq. 90.degree..Type: GrantFiled: December 18, 1991Date of Patent: October 12, 1993Assignees: Kabushiki Kaisha Toshiba, Tokyo Electron LimitedInventors: Shinji Miyazaki, Yuichi Mikata, Takahiko Moriya, Reiji Niino, Motohiko Nishimura
-
Patent number: 5234869Abstract: According to this invention, there is disclosed a method of manufacturing a silicon nitride film on a semiconductor substrate using a low-pressure CVD apparatus, including the steps of setting a plurality of semiconductor wafers in a boat in a reaction furnace, increasing a temperature in the reaction tube to a predetermined temperature and decreasing a pressure in the reaction tube to a predetermined pressure, and supplying Si(N(CH.sub.3).sub.2).sub.4 gas from a first gas source to the reaction tube and supplying NH.sub.3 gas from a second gas source to the reaction tube.Type: GrantFiled: June 26, 1991Date of Patent: August 10, 1993Assignee: Kabushiki Kaisha ToshibaInventors: Yuuichi Mikata, Takahiko Moriya
-
Patent number: 5223455Abstract: A method for forming a refractory metal film on a substrate utilizes a reduction reaction of the halides of the refractory metal with respect to monosilane, disilane, or the halides of monosilane and disilane to form the refractory metal film while suppressing the reaction by adding a hydrogen gas. As a result, the refractory metal film is formed with good quality at a high speed, or deposited selectively on the nitrides, etc., of metal.Type: GrantFiled: May 18, 1992Date of Patent: June 29, 1993Assignee: Kabushiki Kaisha ToshibaInventors: Hitoshi Itoh, Takahiko Moriya
-
Patent number: 5048800Abstract: A vertical heat treatment apparatus includes a reaction furnace constituted by a reaction chamber having an inner tube and an outer tube and a heater arranged outside the reaction chamber, a manifold communicating with a lower portion of the reaction chamber to support the reaction chamber and a gas being supplied and exhausted through the mainfold, a hollow vessel, arranged together with the boat in the reaction furnace, for supporting a lower end of a boat having objects, and a plurality of first heat-insulating members detachably arranged in the hollow vessel, wherein the number of the first insulating members is adjusted to adjust a heat-insulating effect. The first heat-insulating member includes a fin unit constituted by fins horizontally arranged at predetermined intervals and spacers for keeping the intervals between the fins.Type: GrantFiled: August 7, 1990Date of Patent: September 17, 1991Assignees: Kabushiki Kaisha Toshiba, Tokyo Electron Sagami LimitedInventors: Shinji Miyazaki, Takahiko Moriya, Yasushi Yagi, Mituaki Komino, Katuhiko Iwabuchi
-
Patent number: 5015330Abstract: A film forming method comprises the steps of placing a plurality of objects to be processed and supplying an etching gas in a reaction container, removing a natural oxidization originated film on an object to be processed placed in the reaction container under a heating condition by plasma etching, exhausting the etching gas after stopping supply of the etching gas so as to stop making of the plasma, and supplying a film forming gas in the reaction container without rendering the reaction container open to air so as to form a film on the objects.Type: GrantFiled: February 28, 1990Date of Patent: May 14, 1991Assignees: Kabushiki Kaisha Toshiba, Tokyo Electron Limited, Tokyo Electron Sagami LimitedInventors: Katsuya Okumura, Takahiko Moriya, Shinji Miyazaki, Yoshio Kumagai, Susumu Tanaka
-
Patent number: 4957880Abstract: In the production method of a semiconductor device, a connection layer is formed on an insulating layer according to two steps of irradiating, in the atmosphere of a reaction gas, a region in which the connection layer is to be formed selectively by light having a wavelength in a range of from 200 to 1000 nm, and depositing selectively a connection layer forming substrate by a CVD method in the light irradiated region until a desired thickness of the substance is obtained.Type: GrantFiled: April 28, 1989Date of Patent: September 18, 1990Assignee: Kabushiki Kaisha ToshibaInventors: Hitoshi Itoh, Takahiko Moriya
-
Patent number: 4746549Abstract: In a method for forming a thin film of a refractory metal on a substrate having a silicon layer and an insulating layer on a surface thereof, a halogen compound of the refractory metal is mixed with hydrogen gas for providing a material gas, hydrogen halide gas or a halogen gas consisting of a second halogen less electronegative than the first halogen forming the halogen compound of the refractory metal is added to the material gas, and by use of the thus obtained mixed gas, vapor phase deposition refractory metal is effected selectively on the surface of the silicon layer of the substrate.Type: GrantFiled: January 15, 1987Date of Patent: May 24, 1988Assignee: Kabushiki Kaisha ToshibaInventors: Hitoshi Ito, Takahiko Moriya
-
Patent number: 4699801Abstract: A semiconductor device is produced in such a manner that light having a wavelength in a range of 400 to 1000 nm is irradiated on a substrate so as to excite bonding hand of a material gas into a vibrating condition, and a thin film is formed on the substrate in accordance with a chemical vapor deposition method.Type: GrantFiled: February 26, 1986Date of Patent: October 13, 1987Assignee: Kabuskiki Kaisha ToshibaInventors: Hitoshi Ito, Takahiko Moriya
-
Patent number: 4650698Abstract: A method of forming with good reproducibility a high-quality thin film of a metal or metal compound by a vapor growth method on a substrate placed in a quartz reaction tube which has the steps of, prior to the formation of the thin film forming an intermediate film of a material having good adhesion with both quartz, and the metal or metal compound on the inner wall of the reaction tube, and forming a film of the metal or metal compound for the thin film on the intermediate film.Type: GrantFiled: September 26, 1985Date of Patent: March 17, 1987Assignee: Kabushiki Kaisha ToshibaInventors: Takahiko Moriya, Saburo Nakada
-
Patent number: 4597167Abstract: A method of producing a semiconductor device, including the steps of introducing an impurity of one conductivity type into a semiconductor substrate of an opposite conductivity type having an insulating film pattern formed on a surface thereof, using the insulating film pattern as a mask to form a diffusion layer; and forming a metal film on the diffusion layer by selective vapor growth with a mixture of a metal source gas and a carrier gas used as a feed gas. The vapor growth is carried out such that the distance of entry of the metal film from the edge of the insulating film pattern to the interface between the insulating film pattern and the diffusion layer is smaller than the depth of the pn junction of the diffusion layer. The particular method makes it possible to achieve a selective vapor growth of a metal film on the diffusion layer without deteriorating the pn junction characteristics.Type: GrantFiled: August 16, 1984Date of Patent: July 1, 1986Assignee: Kabushiki Kaisha ToshibaInventors: Takahiko Moriya, Saburo Nakada
-
Patent number: 4582563Abstract: First conductive members are buried in first holes formed in a first insulating film to connect the second interconnection layers, formed through first and second insulating films, to a semiconductor substrate. Second conductive members are buried in second holes formed to be positioned on the first holes of the second insulating film. Thus, the reliability of a semiconductor device of a multi-layer interconnection structure is improved, and the integration thereof is improved.Type: GrantFiled: November 28, 1984Date of Patent: April 15, 1986Assignee: Kabushiki Kaisha ToshibaInventors: Yoshikazu Hazuki, Takahiko Moriya
-
Patent number: 4377438Abstract: A method for producing a semiconductor device has the steps of forming an insulating film on an uneven surface of a semiconductor body; and dry etching the insulating film by using as an etchant a gas containing carbon-halogen bonds and hydrogen, whereby the surface of said insulating film is smoothed.Type: GrantFiled: September 22, 1981Date of Patent: March 22, 1983Assignee: Tokyo Shibaura Denki Kabushiki KaishaInventors: Takahiko Moriya, Yoshikazu Hazuki, Masahiro Kashiwagi
-
Patent number: 4283439Abstract: A method of manufacturing a semiconductor device comprises the steps of forming an interconnection electrode made of a refractory metal or a silicide of the metal on an insulating film formed on a semiconductor substrate with necessary elements already formed, forming a silicon nitride film on the interconnection electrode, and forming a silicon oxide film on the silicon nitride film, thereby preventing the elements from being deteriorated.Type: GrantFiled: April 29, 1980Date of Patent: August 11, 1981Assignee: VLSI Technology Research AssociationInventors: Iwao Higashinakagawa, Syohei Sima, Takahiko Moriya
-
Patent number: 4063973Abstract: A non-monocrystalline semiconductor layer which contains predetermined impurities is disposed on a semiconductor substrate. Then, on this semiconductor layer an oxide layer is formed which contains the same type impurities as in the semiconductor layer. The device is then heated at a high temperature, thus causing the impurities to diffuse into the semiconductor substrate and form impurity diffused regions. Suitable electrodes are deposited on the impurity diffused regions.Type: GrantFiled: November 4, 1976Date of Patent: December 20, 1977Assignee: Tokyo Shibaura Electric Co., Ltd.Inventors: Kei Kirita, Yasutaka Tsuji, Takahiko Moriya