Patents by Inventor Takahiko Orita
Takahiko Orita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9514251Abstract: A changing method include: generating, by a computer, a movement track of a figure in response to movement of the figure; detecting an overlap between a line segment and the movement track; and changing, when the overlap is detected, the shape of a portion of the line segment that overlaps the movement track to a shape along an outer periphery of the movement track.Type: GrantFiled: February 20, 2013Date of Patent: December 6, 2016Assignee: FUJITSU LIMITEDInventors: Tomo Kaniwa, Takahiko Orita
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Publication number: 20150195213Abstract: A non-transitory computer-readable recording medium stores therein a program for causing a computer to execute a process. The process includes receiving a request regarding a function that is implemented by a server; and specifying a server to implement a function requested by the received request on the basis of first information that associates one of multiple functions that are implemented by a server with a server that includes hardware necessary to implement the function.Type: ApplicationFiled: December 16, 2014Publication date: July 9, 2015Applicant: Fujitsu LimitedInventor: Takahiko Orita
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Patent number: 8930869Abstract: A wiring-design aiding method for causing a computer to execute generating paths for buses so that the buses do not cross each other with respect to a wiring area including at least one wiring layer, the paths being represented by corresponding graphics The computer further executes verifying, for each bus, whether wires for nets belonging to the bus are successfully extracted from a component to which the bus is connected; and recording, in the wiring area, graphics representing the nets belonging to a bus for which it is determined in the verification that all the nets belonging to the bus are successfully extracted. The bus-path generation is re-executed with respect to the bus for which it is determined in the verification that at least one of the nets is not successfully extracted.Type: GrantFiled: March 30, 2011Date of Patent: January 6, 2015Assignee: Fujitsu LimitedInventors: Ikuo Ohtsuka, Eiichi Konno, Takahiko Orita, Yoshitaka Nishio, Toshiyasu Sakata
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Patent number: 8898615Abstract: A receiving unit receives specification of two parts to be connected by wirings and the number of wirings connecting the two parts. A generating unit generates a schematic route connecting the two parts on a substrate with a width in accordance with the number of wirings received by the receiving unit. A derivation unit derives the number of arrangeable wirings by checking interference whether the schematic route generated by the generating unit is capable of being arranged on the substrate.Type: GrantFiled: November 14, 2013Date of Patent: November 25, 2014Assignee: Fujitsu LimitedInventors: Kazunori Kumagai, Takahiko Orita
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Patent number: 8847971Abstract: A device includes a processor which executes a process including generating data of a second graphic identified by shifting each of first sides of a first graphic by a length in a direction toward an inside of the first graphic and by tracing, in a direction, the first sides after the shifting and intersection points between the first sides after the shifting, generating data of a third graphic by shifting each of second sides of the second graphic to both sides of each of the second side by the length and by linking end points of the second sides after the shifting using a circular arc which is centered on an end point of the second side before the shifting and which has a radius of the length, and generating data of a fourth graphic by performing a logical addition operation between the second graphic and the third graphic.Type: GrantFiled: January 23, 2012Date of Patent: September 30, 2014Assignee: Fujitsu LimitedInventors: Tomo Kaniwa, Takahiko Orita
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Publication number: 20140201696Abstract: A receiving unit receives specification of two parts to be connected by wirings and the number of wirings connecting the two parts. A generating unit generates a schematic route connecting the two parts on a substrate with a width in accordance with the number of wirings received by the receiving unit. A derivation unit derives the number of arrangeable wirings by checking interference whether the schematic route generated by the generating unit is capable of being arranged on the substrate.Type: ApplicationFiled: November 14, 2013Publication date: July 17, 2014Applicant: FUJITSU LIMITEDInventors: Kazunori KUMAGAI, Takahiko ORITA
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Publication number: 20140189631Abstract: A computer-readable recording medium having stored therein a program for causing a computer to execute a circuit design process includes: calculating a maximum number of wirings arrangeable in an adjacent region of a part on a board based on a design rule; and drawing the wirings of the maximum number in the adjacent region of the part on the board.Type: ApplicationFiled: August 14, 2013Publication date: July 3, 2014Applicant: FUJITSU LIMITEDInventors: Toshiyasu Sakata, Takahiko Orita
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Patent number: 8762913Abstract: In a generation method, the computer detects a contact between a pin data group of a first connection destination included in three-dimensional shape data and a pin data group of a first connection source included in three-dimensional shape data of a connector, and determines first contact information that indicates combinations of pin data items of the pin data group of the first connection destination and respective pin data items of the pin data group of the first connection source. Furthermore, the computer detects a contact between a pin data group of a second connection destination and a pin data group of a second connection source, and determines second contact information that indicates combinations of pin data items of the pin data group of the second connection destination and respective pin data items of the pin data group of the second connection source, and generates a connection relationship data group.Type: GrantFiled: February 28, 2013Date of Patent: June 24, 2014Assignee: Fujitsu LimitedInventor: Takahiko Orita
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Patent number: 8667447Abstract: A wiring design apparatus for designing a plurality of wiring lines of a printed circuit board including a plurality of connection posts arranged in a matrix, includes a processor, the processor providing an orthogonal grid including a plurality of rows and columns running over and between the connection posts, providing a plurality of diagonal paths each connecting at least one of the rows with at least one of the columns each running between each of adjacent pairs of the connection posts, and determining a route for each of the wiring lines by exclusively allocating to each of the wiring lines a selected part of the rows, the columns and the paths so that the selected part connects both ends of each of the wiring lines.Type: GrantFiled: February 21, 2013Date of Patent: March 4, 2014Assignee: Fujitsu LimitedInventors: Ikuo Ohtsuka, Takao Yamaguchi, Eiichi Konno, Toshiyasu Sakata, Takahiko Orita
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Publication number: 20130346030Abstract: A changing method include: generating, by a computer, a movement track of a figure in response to movement of the figure; detecting an overlap between a line segment and the movement track; and changing, when the overlap is detected, the shape of a portion of the line segment that overlaps the movement track to a shape along an outer periphery of the movement track.Type: ApplicationFiled: February 20, 2013Publication date: December 26, 2013Applicant: FUJITSU LIMITEDInventors: Tomo KANIWA, Takahiko ORITA
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Publication number: 20130326444Abstract: In a generation method, the computer detects a contact between a pin data group of a first connection destination included in three-dimensional shape data and a pin data group of a first connection source included in three-dimensional shape data of a connector, and determines first contact information that indicates combinations of pin data items of the pin data group of the first connection destination and respective pin data items of the pin data group of the first connection source. Furthermore, the computer detects a contact between a pin data group of a second connection destination and a pin data group of a second connection source, and determines second contact information that indicates combinations of pin data items of the pin data group of the second connection destination and respective pin data items of the pin data group of the second connection source, and generates a connection relationship data group.Type: ApplicationFiled: February 28, 2013Publication date: December 5, 2013Applicant: FUJITSU LIMITEDInventor: Takahiko ORITA
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Patent number: 8539432Abstract: A computer-readable recording medium stores a program that causes a computer to execute a circuit design process. The process includes selecting component data in first board data from among the first board data including first connector component data and second board data including second connector component data that is associated with the first connector component data; setting a connection destination net name of the selected component data to a first vacant terminal of the first connector component data; and setting the connection destination net name of the component data to a second vacant terminal of the second connector component data that corresponds to the first vacant terminal of the first connector data when the component data is moved from the first board data to the second board data.Type: GrantFiled: August 22, 2012Date of Patent: September 17, 2013Assignee: Fujitsu LimitedInventor: Takahiko Orita
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Publication number: 20130132921Abstract: A computer-readable recording medium stores a program that causes a computer to execute a circuit design process. The process includes selecting component data in first board data from among the first board data including first connector component data and second board data including second connector component data that is associated with the first connector component data; setting a connection destination net name of the selected component data to a first vacant terminal of the first connector component data; and setting the connection destination net name of the component data to a second vacant terminal of the second connector component data that corresponds to the first vacant terminal of the first connector data when the component data is moved from the first board data to the second board data.Type: ApplicationFiled: August 22, 2012Publication date: May 23, 2013Applicant: FUJITSU LIMITEDInventor: Takahiko ORITA
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Patent number: 8443333Abstract: A non-transitory computer-readable recording medium storing a design supporting program causes a computer to perform: acquiring non-complying line lengths of a plurality of wiring paths; drawing for each of the wiring paths a wiring pattern connecting a transmission origin and a transmission destination based on a line length and a wiring route of the wiring path; and controlling the drawing to draw a line for each of the wiring paths, the line being divided into a first line amounting to a non-complying line length acquired at the acquiring and a second line being a wiring pass less the non-complying line length.Type: GrantFiled: March 9, 2011Date of Patent: May 14, 2013Assignee: Fujitsu LimitedInventors: Takahiko Orita, Kazunori Kumagai, Yoshitaka Nishio, Ikuo Ohtsuka, Motoyuki Tanisho
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Patent number: 8402422Abstract: A wiring design device to conduct wiring design on a printed wiring board that includes a plurality of conductive layers, the wiring design device including: noise contaminating part extracting means for extracting a part in a condition where noise contaminates a signal, the part being on a wiring-designed line, based on a route of the line and a physical condition around the route; route modification processing means for modifying the route of the line by moving the extracted part on the line in the condition where noise contaminates the signal to a position that avoids the condition where noise contaminates the signal; and line length adjusting means for conducting a line length adjustment on the line to compensate for a variation of the line length of the line when the variation of the line length of the line occurs due to modifying the route of the line.Type: GrantFiled: March 15, 2011Date of Patent: March 19, 2013Assignee: Fujitsu LimitedInventors: Toshiyasu Sakata, Eiichi Konno, Takahiko Orita, Kazunori Kumagai
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Patent number: 8402413Abstract: A wiring design apparatus for designing a plurality of wiring lines of a printed circuit board including a plurality of connection posts arranged in a matrix, includes a processor, the processor providing an orthogonal grid including a plurality of rows and columns running over and between the connection posts, providing a plurality of diagonal paths each connecting at least one of the rows with at least one of the columns each running between each of adjacent pairs of the connection posts, and determining a route for each of the wiring lines by exclusively allocating to each of the wiring lines a selected part of the rows, the columns and the paths so that the selected part connects both ends of each of the wiring lines.Type: GrantFiled: March 11, 2010Date of Patent: March 19, 2013Assignee: Fujitsu LimitedInventors: Ikuo Ohtsuka, Takao Yamaguchi, Eiichi Konno, Toshiyasu Sakata, Takahiko Orita
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Patent number: 8307322Abstract: A wiring design apparatus includes a first acquirer that acquires a first wiring block whose region has a maximum number of crossings with regions of other wiring blocks from printed circuit board data of a printed circuit board having a plurality of wiring blocks with a specific region on a wiring layer, a second acquirer that acquires second wiring blocks whose region does not cross the first wiring block from the printed circuit board data, and a wiring execution requester that causes a wiring processor to perform wiring processing on the first wiring block and the second wiring blocks in parallel.Type: GrantFiled: October 6, 2009Date of Patent: November 6, 2012Assignee: Fujitsu LimitedInventors: Eiichi Konno, Yoshitaka Nishio, Takao Yamaguchi, Toshiyasu Sakata, Takahiko Orita
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Patent number: 8286124Abstract: A printed circuit board design assisting method, device and storage medium are provided. The assisting method includes referring to the position of terminals of a grid array package part, and attributes indicating whether each of the terminals is a power source terminal or a ground terminal, and selecting the power source terminals as a terminal to be researched, searching for a new connection path between the terminal which has been selected, and one of the ground terminals, by way of a first decoupling capacitor, determining whether there is duplication of paths between the new connection path and an connection path between the terminals connected by way of a second decoupling capacitor, changing the position of the second decoupling capacitor if duplication is detected, and re-searching a connection path between the terminals by way of the second decoupling capacitor, which is not in duplicate with the new connection path.Type: GrantFiled: June 21, 2010Date of Patent: October 9, 2012Assignee: Fujitsu LimitedInventors: Toshiyasu Sakata, Eiichi Konno, Takahiko Orita, Yoshitaka Nishio, Kazunori Kumagai
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Publication number: 20120206460Abstract: A device includes a processor which executes a process including generating data of a second graphic identified by shifting each of first sides of a first graphic by a length in a direction toward an inside of the first graphic and by tracing, in a direction, the first sides after the shifting and intersection points between the first sides after the shifting, generating data of a third graphic by shifting each of second sides of the second graphic to both sides of each of the second side by the length and by linking end points of the second sides after the shifting using a circular arc which is centered on an end point of the second side before the shifting and which has a radius of the length, and generating data of a fourth graphic by performing a logical addition operation between the second graphic and the third graphic.Type: ApplicationFiled: January 23, 2012Publication date: August 16, 2012Applicant: Fujitsu LimitedInventors: Tomo Kaniwa, Takahiko Orita
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Publication number: 20110246955Abstract: A wiring-design aiding method for causing a computer to execute generating paths for buses so that the buses do not cross each other with respect to a wiring area including at least one wiring layer, the paths being represented by corresponding graphics The computer further executes verifying, for each bus, whether wires for nets belonging to the bus are successfully extracted from a component to which the bus is connected; and recording, in the wiring area, graphics representing the nets belonging to a bus for which it is determined in the verification that all the nets belonging to the bus are successfully extracted. The bus-path generation is re-executed with respect to the bus for which it is determined in the verification that at least one of the nets is not successfully extracted.Type: ApplicationFiled: March 30, 2011Publication date: October 6, 2011Applicant: FUJITSU LIMITEDInventors: Ikuo OHTSUKA, Eiichi Konno, Takahiko Orita, Yoshitaka Nishio, Toshiyasu Sakata