Abstract: A failure prediction system includes: a processor, the processor being configured to: collect torque values of a drive axis of a robot that is operating in accordance with a given work program; derive an evaluation formula approximating a time change of the torque value which is most recent from among the collected torque values set a failure threshold that is the torque value at which it is determined that failure of the drive axis occurs, based on the evaluation formula and the time change of the torque value when the drive axis reached failure in the past; and calculate an estimated value for the torque value when a prediction time set in advance has elapsed in the evaluation formula, and determines whether failure of the drive axis is predicted within the prediction time according to comparison between the estimated value and the failure threshold.

Abstract: A failure prediction system according to an aspect of the present disclosure includes: a torque value collection unit which collects torque values of a drive axis of a robot that is operating in accordance with a given work program; an evaluation formula derivation unit which derives an evaluation formula approximating a time change of the torque value which is most recent from among the torque values collected by the torque value collection unit; a threshold setting unit which sets a failure threshold that is the torque value at which it is determined that failure of the drive axis occurs, based on the evaluation formula and the time change of the torque value when the drive axis reached failure in the past; and a prediction determination unit which calculates an estimated value for the torque value when a prediction time set in advance has elapsed in the evaluation formula, and determines whether failure of the drive axis is predicted within the prediction time according to comparison between the estimated

Abstract: A semiconductor device includes a power source selection circuit configured to turn on and off each of a plurality of power source switches. The power source selection circuit includes a power source selection unit configured to select one power source from among the plurality of power sources, and a feedback control unit configured to output an on command signal to turn on an electrical connection between the selected power source and the electric circuit to a power source switch to be connected to the selected power source. When the power source selection unit switches a power source to select to another, the feedback control unit feeds back a signal indicative of that an off command signal to turn off electrical connections between the plurality of power sources and the electric circuit has been output to all of the plurality of power source switches at a predetermined delay time.

Abstract: An operation processing apparatus includes an operation processing unit to perform an operation process using first data administered by the own operation processing apparatus and second data acquired from another operation processing apparatus; a main memory to store the first data; and a control unit to include a storing unit to store status of data indicating whether or not the first data is held by another operation processing apparatus and a indicating unit to indicate a transition between the status in which the first data is held by another operation processing apparatus and the status in which the first data is not held thereby, wherein when the indicating unit indicates that the first data is not held by another operation processing apparatus and a data acquisition request occurs for the first data, the control unit skips a process for referring to the status of use of the first data.

Abstract: An operation processing apparatus connected with another operation processing apparatus including an operation processing unit to perform an operation process using first data administered by the own operation processing apparatus and second data administered by and acquired from another operation processing apparatus, a main memory to store the first data, and a control unit to include a setting unit which sets the operation processing unit to an operating state or a non-operating state and a cache memory which holds the first and second data, wherein when the setting unit sets the operation processing unit to the non-operating state and receives a notification related to discarding of the first data from another operation processing apparatus, the control unit acquires the first data from the main memory and holds the acquired data in the cache memory.

Abstract: When using a read circuit of a semiconductor memory device to read data in a memory cell through a bit line BLX, out of a bit line pair BL, BLX that have a complementary relationship to each other and are connected to the memory cell storing the data, control is performed by a discharge circuit disposed within the read circuit, based on the signal from the bit line BL and a signal indicating the memory cell, to prevent a rise in potential of an SOUT node of the read circuit, or to prevent a fall in potential of the SOUT node, according to the potentials of the bit line pair BL, BLX. The SOUT accordingly does not become a floating node, enabling reading malfunction due to leak current to be prevented and enabling increased reading speed.

Abstract: An operation processing apparatus connected with another operation processing apparatus includes an operation processing unit configured to perform an operation process using first data administered by the own operation processing apparatus and second data administered by another operation processing apparatus and acquired from another operation processing apparatus, and a control unit configured to include a setting unit which sets the operation processing unit to an operating state or a non-operating state and a cache memory which holds the first data and the second data, wherein when the setting unit sets the operation processing unit to the operating state and the second data is evicted from the cache memory, the control unit sends to another operation processing apparatus the evicted data and a request which is a trigger for storing the evicted data in a cache memory in another operation processing apparatus.

Abstract: An operation processing apparatus includes an operation processing unit configured to perform an operation process using first data administered by the own operation processing apparatus and second data administered by and acquired from another operation processing apparatus, a main memory configured to store the first data and third data, and a control unit configured to include a setting unit which sets the operation processing unit to an operating state or a non-operating state and a cache memory which holds the first, second and third data, wherein when the setting unit sets the operation processing unit to the non-operating state and the third data is requested from another operation processing apparatus, which triggers cache miss in the cache memory, the control unit reads the requested data from the main memory and holds the requested data in the cache memory and sends the read data to another operation processing apparatus.

Abstract: A semiconductor device includes a power source selection circuit configured to turn on and off each of a plurality of power source switches. The power source selection circuit includes a power source selection unit configured to select one power source from among the plurality of power sources, and a feedback control unit configured to output an on command signal to turn on an electrical connection between the selected power source and the electric circuit to a power source switch to be connected to the selected power source. When the power source selection unit switches a power source to select to another, the feedback control unit feeds back a signal indicative of that an off command signal to turn off electrical connections between the plurality of power sources and the electric circuit has been output to all of the plurality of power source switches at a predetermined delay time.

Abstract: According to the ultrawideband communication antenna, since surfaces of the antenna element are coated with the first resin layer and the second resin layer each of which is mixed with the nonmagnetic metal powder and has an insulating property and a high specific inductive capacity, the size is largely reduced. Further, since the nonmagnetic metal powder is used, the first resin layer and the second resin layer are free from a loss of magnetism generated therein, thereby enabling to maintain a loss of the antenna to a low level.

Abstract: According to the ultrawideband communication antenna, since surfaces of the antenna element are coated with the first resin layer and the second resin layer each of which is mixed with the nonmagnetic metal powder and has an insulating property and a high specific inductive capacity, the size is largely reduced. Further, since the nonmagnetic metal powder is used, the first resin layer and the second resin layer are free from a loss of magnetism generated therein, thereby enabling to maintain a loss of the antenna to a low level.