Abstract: In order to control the resetting operation, a mobile phone is provided with a CPU capable of executing an application program, a power switch to receive an instruction for switching power between the ON state and the OFF state, and a reset detecting circuit to output a resetting signal for rebooting the CPU when the power switch is closed for a predetermined period of time. The CPU outputs a state signal denoting either a resettable state or a non-resettable state of the CPU. The reset detecting circuit includes an AND element to output to a resetting circuit a high signal (resetting signal) on condition that the state signal denotes the state of the CPU as resettable. The resetting circuit outputs to the CPU a low signal (resetting signal) upon input of the high signal (resetting signal) from the reset detecting circuit.

Abstract: In order to control the resetting operation, a mobile phone is provided with a CPU capable of executing an application program, a power switch to receive an instruction for switching power between the ON state and the OFF state, and a reset detecting circuit to output a resetting signal for rebooting the CPU when the power switch is closed for a predetermined period of time. The CPU outputs a state signal denoting either a resettable state or a non-resettable state of the CPU. The reset detecting circuit includes an AND element to output to a resetting circuit a high signal (resetting signal) on condition that the state signal denotes the state of the CPU as resettable. The resetting circuit outputs to the CPU a low signal (resetting signal) upon input of the high signal (resetting signal) from the reset detecting circuit.