Abstract: A time-series data prediction device includes an acquisition unit, a prediction model generation unit, and a prediction unit. The acquisition unit acquires a plurality of observation values that continue at predetermined time intervals, as a prediction data, from time-series data of an observation value of a predetermined observation target, and acquires a training data. The prediction model generation unit generates a prediction model to calculate time-series data, which is an observation value predicted based on given time-series data, using the training data. The prediction unit calculates a predicted value of an observation value using the generated prediction model and the prediction data.

Abstract: A performance predicting apparatus includes an approximate model storage unit configured to store approximate models each of which is associated with one of categories, and which are used to calculate functional performance based on feature values, a feature value extracting unit configured to extract the feature values from shape data representing a shape of an object, a selection unit configured to select one of the approximate models to be used from the approximate models stored in the approximate model storage unit depending on the feature values extracted by the feature value extracting unit, and a performance calculating unit configured to calculate functional performance based on the feature values extracted by the feature value extracting unit using the approximate model selected by the selection unit.

Abstract: A time-series data prediction device includes an acquisition unit, a prediction model generation unit, and a prediction unit. The acquisition unit acquires a plurality of observation values that continue at predetermined time intervals, as a prediction data, from time-series data of an observation value of a predetermined observation target, and acquires a training data. The prediction model generation unit generates a prediction model to calculate time-series data, which is an observation value predicted based on given time-series data, using the training data. The prediction unit calculates a predicted value of an observation value using the generated prediction model and the prediction data.

Abstract: A performance predicting apparatus includes an approximate model storage unit configured to store approximate models each of which is associated with one of categories, and which are used to calculate functional performance based on feature values, a feature value extracting unit configured to extract the feature values from shape data representing a shape of an object, a selection unit configured to select one of the approximate models to be used from the approximate models stored in the approximate model storage unit depending on the feature values extracted by the feature value extracting unit, and a performance calculating unit configured to calculate functional performance based on the feature values extracted by the feature value extracting unit using the approximate model selected by the selection unit.

Abstract: Disclosed herein is a storage device including: a communication execution unit configured to be capable of controlling an operation state between a communication-enabled state in which data communication is possible and a pause state in which data communication is impossible; a buffer configured to store data transmitted and received by the communication execution unit; a memory configured to be capable of storing data; a memory controller configured to carry out data input and output between the memory and the buffer; and a communication controller configured to make the communication execution unit operate if data communication is carried out, and make the communication execution unit take a pause if data communication is not carried out. The communication controller switches the operation state of the communication execution unit between the communication-enabled state and the pause state in data communication depending on a data processing state of the buffer.

Abstract: Disclosed herein is a storage device including: a communication execution unit configured to be capable of controlling an operation state between a communication-enabled state in which data communication is possible and a pause state in which data communication is impossible; a buffer configured to store data transmitted and received by the communication execution unit; a memory configured to be capable of storing data; a memory controller configured to carry out data input and output between the memory and the buffer; and a communication controller configured to make the communication execution unit operate if data communication is carried out, and make the communication execution unit take a pause if data communication is not carried out. The communication controller switches the operation state of the communication execution unit between the communication-enabled state and the pause state in data communication depending on a data processing state of the buffer.

Abstract: A nonvolatile-memory controlling method is disclosed which continuously accesses a plurality of memory banks structured so as to have each memory bank accessible independently. The method comprises the steps of: in a busy cycle of one of the plurality of memory banks being accessed, issuing access information to a second memory bank for access thereto; bringing the second memory bank into a selected state while the access information is being issued to the second memory bank using a selection signal for controlling a selected state and an unselected state for any one of the plurality of memory banks; bringing the memory bank in the busy cycle into an unselected state while the access information is being issued; and accessing the plurality of memory banks continuously based on the access information issued to the second memory bank in the busy cycle of one of the memory banks being accessed and in keeping with the selection signal for controlling the second memory bank.

Abstract: The present invention has been made to realize a storage device capable of normally reading out data from the erase processing applied area. In a semiconductor storage device 1, when data read processing is performed for the erase-processing applied area in a memory section 2 to read out erase-state actual data Ddr and erase-state parity data Ddp each containing only “1s”, the erase-state actual data Ddr and erase-state parity data Ddp are inverted by a third data inverting circuit 13 to make all the values thereof “0”, followed by execution of the error detection processing. With the above configuration, it is possible to prevent an error from being detected in the error detection processing.

Abstract: The present invention has been made to realize a storage device capable of normally reading out data from the erase processing applied area. In a semiconductor storage device 1, when data read processing is performed for the erase-processing applied area in a memory section 2 to read out erase-state actual data Ddr and erase-state parity data Ddp each containing only “1s”, the erase-state actual data Ddr and erase-state parity data Ddp are inverted by a third data inverting circuit 13 to make all the values thereof “0”, followed by execution of the error detection processing. With the above configuration, it is possible to prevent an error from being detected in the error detection processing.

Abstract: A nonvolatile-memory controlling method is disclosed which continuously accesses a plurality of memory banks structured so as to have each memory bank accessible independently. The method comprises the steps of: in a busy cycle of one of the plurality of memory banks being accessed, issuing access information to a second memory bank for access thereto; bringing the second memory bank into a selected state while the access information is being issued to the second memory bank using a selection signal for controlling a selected state and an unselected state for any one of the plurality of memory banks; bringing the memory bank in the busy cycle into an unselected state while the access information is being issued; and accessing the plurality of memory banks continuously based on the access information issued to the second memory bank in the busy cycle of one of the memory banks being accessed and in keeping with the selection signal for controlling the second memory bank.