Abstract: An address transition detecting circuit detects on address transition signal generated during the writing of input data into a static random access memory (SRAM) and generates an address detection signal as a monostable pulse of a predetermined length. A bit line precharge and equalize signals generating circuit generates, in synchronization with the address transition detection signal and an input signal on a write data line, a bit line precharge signal and bit line equalize signal which are supplied to their columns in memory. At a time of reading, the bit line precharge and equalize signals generating circuit supplies a high level potential to paired data lines to prevent a data entry from being made into the paired write data lines by a resetting operation.

Abstract: A main row decoder for driving main word lines in a main memory cell array includes partial decoders the number of which is equal to the number of the main word lines. Each partial decoder includes a NAND gate for receiving row address signals, an inverter for driving a corresponding main word line in response to an output from the NAND gate, a fuse element connected between the output terminal of the NAND gate and the input terminal of the inverter, and a MOS transistor connected between the input terminal of the inverter and a power supply voltage.