Abstract: The present invention provides an access controller, and a data transfer method. The access controller controls accesses to the MRAM by reading data in advance and backing up the data when data is to be read from the MRAM.

Abstract: The present invention provides a device with low power and high performance, which can be applied to sensor nodes, a sensor node using the same, an access controller, a data transfer method, and execute a processing method in a microcontroller. The device has: an MRAM; a non-volatile CPU configured to include a nonvolatile memory; a non-volatile FPGA-ACC configured to include a nonvolatile memory and execute a part of operations on the nonvolatile CPU; and a power-gating control unit that controls power supply to each memory cell in the MRAM, the non-volatile CPU, and the non-volatile FPGA-ACC. The device is further provided with an access controller that controls accesses to the MRAM by reading data in advance and backing up the data when data is to be read from the MRAM.

Abstract: A processing circuit according to an embodiment includes a plurality of logic gates in combination each of which is configured to probabilistically determine, based on signal values of one or two or more input nodes and output nodes at a certain time, signal values at at least one of the input nodes and the output nodes at a subsequent time, in which the processing circuit controls the signal values based on a relationship to be satisfied between at least some nodes of the input nodes and the output nodes.

Abstract: A nonvolatile logic circuit includes: a memory unit having a pair of resistive memory elements; a computation unit connected to the memory unit and configured to perform an operation based on an input signal and a logic value corresponding to a resistance state of the pair of resistive memory elements; a determination circuit configured to determine whether the resistance state of the pair of resistive memory elements is a complementary state or a non-complementary state; and an output circuit connected to the computation unit and the determination circuit, and configured to output a signal corresponding to an operation result by the computation unit or a signal corresponding to a determination result by the determination circuit.

Abstract: A lookup table circuit constituting a programmable logic device includes: a memory cell array including a plurality of memory cells, each having a resistive memory element; a selection circuit connected to the memory cell array and configured to output, to the memory cell array, a single cell-select signal or two or more cell-select signals for selecting a single memory cell or two or more memory cells among the plurality of memory cells, based on input of a plurality of logic signals; and a read circuit connected to the memory cell array and configured to read data from the single memory cell or the two or more memory cells selected by the single cell-select signal or the two or more cell-select signals, among the plurality of memory cells. The selection circuit is separated from a path along which the read circuit is configured to read data from the memory cell array.

Abstract: A memory circuit device includes multiple memory cells that are each constituted of a resistive memory element, a write circuit unit that is configured to write data to any one of the memory cells which is designated by cell designating information, and a read circuit unit that is configured to read out, from the memory cell designated by the cell designating information, data written in the memory cell. The memory circuit device has a configuration including a selection circuit unit that is shared by both of the write circuit unit and the read circuit unit and configured to select a memory cell to be activated from the multiple memory cells based on the cell designating information, and a control circuit unit that is configured to selectively enable any one of writing of data by the write circuit unit and reading of data by the read circuit unit with respect to the memory cell selected by the selection circuit unit.

Abstract: A random number generator according to one embodiment includes a write circuit, a read circuit, and a signal output circuit. The write circuit inverts magnetization of a magnetic layer of a magnetic tunnel junction element stochastically by supplying current to the magnetic layer. The read circuit reads the magnetization. The signal output circuit generates a random number on the basis of the magnetization read by the read circuit. The random number generator includes a sequence control circuit that controls the write circuit and the read circuit. The sequence control circuit regulates the write circuit to supply the current to the write circuit in a first period, and causes the read circuit to read the magnetization after the first period is finished and then a second period longer than the first period is elapsed.

Abstract: The present invention provides a device with low power and high performance, which can be applied to sensor nodes, a sensor node using the same, an access controller, a data transfer method, and execute a processing method in a microcontroller. The device has: an MRAM; a non-volatile CPU configured to include a nonvolatile memory; a non-volatile FPGA-ACC configured to include a nonvolatile memory and execute a part of operations on the nonvolatile CPU; and a power-gating control unit that controls power supply to each memory cell in the MRAM, the non-volatile CPU, and the non-volatile FPGA-ACC. The device is further provided with an access controller that controls accesses to the MRAM by reading data in advance and backing up the data when data is to be read from the MRAM.

Abstract: A nonvolatile logic circuit includes: a memory unit having a pair of resistive memory elements; a computation unit connected to the memory unit and configured to perform an operation based on an input signal and a logic value corresponding to a resistance state of the pair of resistive memory elements; a determination circuit configured to determine whether the resistance state of the pair of resistive memory elements is a complementary state or a non-complementary state; and an output circuit connected to the computation unit and the determination circuit, and configured to output a signal corresponding to an operation result by the computation unit or a signal corresponding to a determination result by the determination circuit.

Abstract: A memory circuit device includes multiple memory cells that are each constituted of a resistive memory element, a write circuit unit that is configured to write data to any one of the memory cells which is designated by cell designating information, and a read circuit unit that is configured to read out, from the memory cell designated by the cell designating information, data written in the memory cell. The memory circuit device has a configuration including a selection circuit unit that is shared by both of the write circuit unit and the read circuit unit and configured to select a memory cell to be activated from the multiple memory cells based on the cell designating information, and a control circuit unit that is configured to selectively enable any one of writing of data by the write circuit unit and reading of data by the read circuit unit with respect to the memory cell selected by the selection circuit unit.

Abstract: A memory circuit device includes multiple memory cells that are each constituted of a resistive memory element; a write circuit unit that is configured to write data to any one of the memory cells which is designated by cell designating information, and a read circuit unit that is configured to read out, from the memory cell designated by the cell designating information, data written in the memory cell. The memory circuit device has a configuration including a selection circuit unit that is shared by both of the write circuit unit and the read circuit unit and configured to select a memory cell to be activated from the multiple memory cells based on cell designating information, and a control circuit unit that is configured to selectively enable any one of writing of data by the write circuit unit and reading of data by the read circuit unit with respect to the memory cell selected by the selection circuit unit.

Abstract: A data write device for a resistive memory element, the resistive memory element including: a conductive electrode provided at one end of the memory element; and a reading electrode provided at the other end of the memory element being configured to vary a resistance of the memory element by applying a write current to the conductive electrode, the data write device for the resistive memory element further includes: a writing means, an output means, and a control means. The output means is provided between a power supply and the reading electrode. As output signals, a read signal from the memory element and a monitor signal to monitor a writing status of the memory element written by the writing means are output from the output means. By the monitor signal, a termination of data-writing into the resistive memory element is detected.

Abstract: A lookup table circuit constituting a programmable logic device includes: a memory cell array including a plurality of memory cells, each having a resistive memory element; a selection circuit connected to the memory cell array and configured to output, to the memory cell array, a single cell-select signal or two or more cell-select signals for selecting a single memory cell or two or more memory cells among the plurality of memory cells, based on input of a plurality of logic signals; and a read circuit connected to the memory cell array and configured to read data from the single memory cell or the two or more memory cells selected by the single cell-select signal or the two or more cell-select signals, among the plurality of memory cells. The selection circuit is separated from a path along which the read circuit is configured to read data from the memory cell array.

Abstract: A random number generator according to one embodiment includes a write circuit, a read circuit, and a signal output circuit. The write circuit inverts magnetization of a magnetic layer of a magnetic tunnel junction element stochastically by supplying current to the magnetic layer. The read circuit reads the magnetization. The signal output circuit generates a random number on the basis of the magnetization read by the read circuit. The random number generator includes a sequence control circuit that controls the write circuit and the read circuit. The sequence control circuit regulates the write circuit to supply the current to the write circuit in a first period, and causes the read circuit to read the magnetization after the first period is finished and then a second period longer than the first period is elapsed.

Abstract: A data write circuit of a resistive memory element is provided, the device being capable of writing with low writing energy using a simple circuit. The data write circuit of the resistive memory element, includes: a complementary resistive memory element; writing means for making the complementary resistive memory element cause a resistance change; detection means for detecting a writing state in the complementary resistive memory element; and control means for controlling writing by the writing means, based on a detected signal of the detection means.

Abstract: In reading of a memory unit, an read failure operation due to variation in characteristic of a transistor in a dynamic load is reduced. A read circuit that reads a voltage obtained by a voltage division of a dynamic load unit and the memory unit as an output of the memory unit includes the dynamic load unit having one end connected to a side of a power supply and the other end connected to a side of the memory unit, and a feedback unit that, by a feedback of the voltage obtained by the voltage division that is divided between the dynamic load unit and the memory unit, holds the voltage obtained by the voltage division. The dynamic load unit has an array structure in which a plurality of resistive memory elements are connected in series, in parallel, or in series-parallel. The dynamic load unit has the array structure of the resistive memory elements and this structure can suppress the read failure operation due to the variation in dynamic load.

Abstract: A circuit design support system, a circuit design support method, a circuit design support program, and a recording medium having the program recorded thereon are provided by which a design can be performed in consideration of the stochastic operation of the stochastic operation element and the influence caused by the stochastic operation of the stochastic operation element on the operation reliability of the circuit can be evaluated.

Abstract: A memory circuit device includes multiple memory cells that are each constituted of a resistive memory element; a write circuit unit that is configured to write data to any one of the memory cells which is designated by cell designating information, and a read circuit unit that is configured to read out, from the memory cell designated by the cell designating information, data written in the memory cell. The memory circuit device has a configuration including a selection circuit unit that is shared by both of the write circuit unit and the read circuit unit and configured to select a memory cell to be activated from the multiple memory cells based on cell designating information, and a control circuit unit that is configured to selectively enable any one of writing of data by the write circuit unit and reading of data by the read circuit unit with respect to the memory cell selected by the selection circuit unit.

Abstract: A data write device for a resistive memory element, the resistive memory element including: a conductive electrode provided at one end of the memory element; and a reading electrode provided at the other end of the memory element being configured to vary a resistance of the memory element by applying a write current to the conductive electrode, the data write device for the resistive memory element further includes: a writing means, an output means, and a control means. The output means is provided between a power supply and the reading electrode. As output signals, a read signal from the memory element and a monitor signal to monitor a writing status of the memory element written by the writing means are output from the output means. By the monitor signal, a termination of data-writing into the resistive memory element is detected.

Abstract: A data write circuit of a resistive memory element is provided, the device being capable of writing with low writing energy using a simple circuit. The data write circuit of the resistive memory element, includes: a complementary resistive memory element; writing means for making the complementary resistive memory element cause a resistance change; detection means for detecting a writing state in the complementary resistive memory element; and control means for controlling writing by the writing means, based on a detected signal of the detection means.