Patents by Inventor Takahiro Hanyu

Takahiro Hanyu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220076722
    Abstract: A nonvolatile logic circuit includes: a memory unit having a pair of resistive memory elements; a computation unit connected to the memory unit and configured to perform an operation based on an input signal and a logic value corresponding to a resistance state of the pair of resistive memory elements; a determination circuit configured to determine whether the resistance state of the pair of resistive memory elements is a complementary state or a non-complementary state; and an output circuit connected to the computation unit and the determination circuit, and configured to output a signal corresponding to an operation result by the computation unit or a signal corresponding to a determination result by the determination circuit.
    Type: Application
    Filed: November 28, 2019
    Publication date: March 10, 2022
    Inventors: Masanori Natsui, Takahiro Hanyu, Tetsuo Endoh
  • Publication number: 20220059149
    Abstract: A memory circuit device includes multiple memory cells that are each constituted of a resistive memory element, a write circuit unit that is configured to write data to any one of the memory cells which is designated by cell designating information, and a read circuit unit that is configured to read out, from the memory cell designated by the cell designating information, data written in the memory cell. The memory circuit device has a configuration including a selection circuit unit that is shared by both of the write circuit unit and the read circuit unit and configured to select a memory cell to be activated from the multiple memory cells based on the cell designating information, and a control circuit unit that is configured to selectively enable any one of writing of data by the write circuit unit and reading of data by the read circuit unit with respect to the memory cell selected by the selection circuit unit.
    Type: Application
    Filed: November 3, 2021
    Publication date: February 24, 2022
    Inventors: Takahiro Hanyu, Daisuke Suzuki, Hideo Ohno, Tetsuo Endoh
  • Patent number: 11183228
    Abstract: A memory circuit device includes multiple memory cells that are each constituted of a resistive memory element; a write circuit unit that is configured to write data to any one of the memory cells which is designated by cell designating information, and a read circuit unit that is configured to read out, from the memory cell designated by the cell designating information, data written in the memory cell. The memory circuit device has a configuration including a selection circuit unit that is shared by both of the write circuit unit and the read circuit unit and configured to select a memory cell to be activated from the multiple memory cells based on cell designating information, and a control circuit unit that is configured to selectively enable any one of writing of data by the write circuit unit and reading of data by the read circuit unit with respect to the memory cell selected by the selection circuit unit.
    Type: Grant
    Filed: September 14, 2018
    Date of Patent: November 23, 2021
    Assignee: TOHOKU UNIVERSITY
    Inventors: Takahiro Hanyu, Daisuke Suzuki, Hideo Ohno, Tetsuo Endoh
  • Patent number: 11133046
    Abstract: A data write device for a resistive memory element, the resistive memory element including: a conductive electrode provided at one end of the memory element; and a reading electrode provided at the other end of the memory element being configured to vary a resistance of the memory element by applying a write current to the conductive electrode, the data write device for the resistive memory element further includes: a writing means, an output means, and a control means. The output means is provided between a power supply and the reading electrode. As output signals, a read signal from the memory element and a monitor signal to monitor a writing status of the memory element written by the writing means are output from the output means. By the monitor signal, a termination of data-writing into the resistive memory element is detected.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: September 28, 2021
    Assignee: TOHOKU UNIVERSITY
    Inventors: Takahiro Hanyu, Daisuke Suzuki, Hideo Ohno, Tetsuo Endoh
  • Publication number: 20210193206
    Abstract: A lookup table circuit constituting a programmable logic device includes: a memory cell array including a plurality of memory cells, each having a resistive memory element; a selection circuit connected to the memory cell array and configured to output, to the memory cell array, a single cell-select signal or two or more cell-select signals for selecting a single memory cell or two or more memory cells among the plurality of memory cells, based on input of a plurality of logic signals; and a read circuit connected to the memory cell array and configured to read data from the single memory cell or the two or more memory cells selected by the single cell-select signal or the two or more cell-select signals, among the plurality of memory cells. The selection circuit is separated from a path along which the read circuit is configured to read data from the memory cell array.
    Type: Application
    Filed: September 7, 2018
    Publication date: June 24, 2021
    Inventors: Takahiro Hanyu, Daisuke Suzuki, Tetsuo Endoh
  • Publication number: 20210117159
    Abstract: A random number generator according to one embodiment includes a write circuit, a read circuit, and a signal output circuit. The write circuit inverts magnetization of a magnetic layer of a magnetic tunnel junction element stochastically by supplying current to the magnetic layer. The read circuit reads the magnetization. The signal output circuit generates a random number on the basis of the magnetization read by the read circuit. The random number generator includes a sequence control circuit that controls the write circuit and the read circuit. The sequence control circuit regulates the write circuit to supply the current to the write circuit in a first period, and causes the read circuit to read the magnetization after the first period is finished and then a second period longer than the first period is elapsed.
    Type: Application
    Filed: September 11, 2020
    Publication date: April 22, 2021
    Applicants: TOHOKU UNIVERSITY, CANON MEDICAL SYSTEMS CORPORATION
    Inventors: Takahiro HANYU, Naoya ONIZAWA, Akira TAMAKOSHI, Hiroyuki FUJITA, Hitoshi YAMAGATA
  • Patent number: 10896729
    Abstract: A data write circuit of a resistive memory element is provided, the device being capable of writing with low writing energy using a simple circuit. The data write circuit of the resistive memory element, includes: a complementary resistive memory element; writing means for making the complementary resistive memory element cause a resistance change; detection means for detecting a writing state in the complementary resistive memory element; and control means for controlling writing by the writing means, based on a detected signal of the detection means.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: January 19, 2021
    Assignee: TOHOKU UNIVERSITY
    Inventors: Takahiro Hanyu, Daisuke Suzuki, Hideo Ohno, Tetsuo Endoh
  • Patent number: 10783294
    Abstract: A circuit design support system, a circuit design support method, a circuit design support program, and a recording medium having the program recorded thereon are provided by which a design can be performed in consideration of the stochastic operation of the stochastic operation element and the influence caused by the stochastic operation of the stochastic operation element on the operation reliability of the circuit can be evaluated.
    Type: Grant
    Filed: August 3, 2017
    Date of Patent: September 22, 2020
    Assignee: TOHOKU UNIVERSITY
    Inventors: Masanori Natsui, Akira Tamakoshi, Takahiro Hanyu, Akira Mochizuki, Tetsuo Endoh, Hiroki Koike, Hideo Ohno
  • Patent number: 10783936
    Abstract: In reading of a memory unit, an read failure operation due to variation in characteristic of a transistor in a dynamic load is reduced. A read circuit that reads a voltage obtained by a voltage division of a dynamic load unit and the memory unit as an output of the memory unit includes the dynamic load unit having one end connected to a side of a power supply and the other end connected to a side of the memory unit, and a feedback unit that, by a feedback of the voltage obtained by the voltage division that is divided between the dynamic load unit and the memory unit, holds the voltage obtained by the voltage division. The dynamic load unit has an array structure in which a plurality of resistive memory elements are connected in series, in parallel, or in series-parallel. The dynamic load unit has the array structure of the resistive memory elements and this structure can suppress the read failure operation due to the variation in dynamic load.
    Type: Grant
    Filed: December 8, 2017
    Date of Patent: September 22, 2020
    Assignee: TOHOKU UNIVERSITY
    Inventors: Takahiro Hanyu, Daisuke Suzuki, Hideo Ohno, Tetsuo Endoh
  • Publication number: 20200265883
    Abstract: A memory circuit device includes multiple memory cells that are each constituted of a resistive memory element; a write circuit unit that is configured to write data to any one of the memory cells which is designated by cell designating information, and a read circuit unit that is configured to read out, from the memory cell designated by the cell designating information, data written in the memory cell. The memory circuit device has a configuration including a selection circuit unit that is shared by both of the write circuit unit and the read circuit unit and configured to select a memory cell to be activated from the multiple memory cells based on cell designating information, and a control circuit unit that is configured to selectively enable any one of writing of data by the write circuit unit and reading of data by the read circuit unit with respect to the memory cell selected by the selection circuit unit.
    Type: Application
    Filed: September 14, 2014
    Publication date: August 20, 2020
    Inventors: Takahiro Hanyu, Daisuke Suzuki, Hideo Ohno, Tetsuo Endoh
  • Publication number: 20200211611
    Abstract: A data write device for a resistive memory element, the resistive memory element including: a conductive electrode provided at one end of the memory element; and a reading electrode provided at the other end of the memory element being configured to vary a resistance of the memory element by applying a write current to the conductive electrode, the data write device for the resistive memory element further includes: a writing means, an output means, and a control means. The output means is provided between a power supply and the reading electrode. As output signals, a read signal from the memory element and a monitor signal to monitor a writing status of the memory element written by the writing means are output from the output means. By the monitor signal, a termination of data-writing into the resistive memory element is detected.
    Type: Application
    Filed: October 31, 2017
    Publication date: July 2, 2020
    Applicant: TOHOKU UNIVERSITY
    Inventors: Takahiro Hanyu, Daisuke Suzuki, Hideo Ohno, Tetsuo Endoh
  • Publication number: 20200082884
    Abstract: A data write circuit of a resistive memory element is provided, the device being capable of writing with low writing energy using a simple circuit. The data write circuit of the resistive memory element, includes: a complementary resistive memory element; writing means for making the complementary resistive memory element cause a resistance change; detection means for detecting a writing state in the complementary resistive memory element; and control means for controlling writing by the writing means, based on a detected signal of the detection means.
    Type: Application
    Filed: October 31, 2017
    Publication date: March 12, 2020
    Inventors: TAKAHIRO HANYU, DAISUKE SUZUKI, HIDEO OHNO, TETSUO ENDOH
  • Publication number: 20190371370
    Abstract: In reading of a memory unit, an read failure operation due to variation in characteristic of a transistor in a dynamic load is reduced. A read circuit that reads a voltage obtained by a voltage division of a dynamic load unit and the memory unit as an output of the memory unit includes the dynamic load unit having one end connected to a side of a power supply and the other end connected to a side of the memory unit, and a feedback unit that, by a feedback of the voltage obtained by the voltage division that is divided between the dynamic load unit and the memory unit, holds the voltage obtained by the voltage division. The dynamic load unit has an array structure in which a plurality of resistive memory elements are connected in series, in parallel, or in series-parallel. The dynamic load unit has the array structure of the resistive memory elements and this structure can suppress the read failure operation due to the variation in dynamic load.
    Type: Application
    Filed: December 18, 2017
    Publication date: December 5, 2019
    Inventors: Takahiro Hanyu, Daisuke Suzuki, Hideo Ohno, Tetsuo Endoh
  • Publication number: 20190243929
    Abstract: A circuit design support system, a circuit design support method, a circuit design support program, and a recording medium having the program recorded thereon are provided by which a design can be performed in consideration of the stochastic operation of the stochastic operation element and the influence caused by the stochastic operation of the stochastic operation element on the operation reliability of the circuit can be evaluated.
    Type: Application
    Filed: August 3, 2017
    Publication date: August 8, 2019
    Applicant: TOHOKU UNIVERSITY
    Inventors: Masanori NATSUI, Akira TAMAKOSHI, Takahiro HANYU, Akira MOCHIZUKI, Tetsuo ENDOH, Hiroki KOIKE, Hideo OHNO
  • Patent number: 9928906
    Abstract: A data-write device includes a write driver that causes a current to flow through a current path including an MTJ element or the other current path including the MTJ element in accordance with writing data to be written, thereby writing the write data into the MTJ element, a write completion detector which monitors the voltage at a first connection node or a second connection node in accordance with the write data after the writing of the write data into the MTJ element starts, detects the completion of writing of the write data based on the voltage at either node, and supplies a write completion signal indicating the completion of data write, and a write controller that terminates the writing of the write data into the MTJ element in response to the write completion signal supplied from the write completion detector.
    Type: Grant
    Filed: March 24, 2015
    Date of Patent: March 27, 2018
    Assignee: Tohoku University
    Inventors: Takahiro Hanyu, Daisuke Suzuki, Masanori Natsui, Akira Mochizuki, Hideo Ohno, Tetsuo Endoh
  • Publication number: 20170365338
    Abstract: A data-write device includes a write driver that causes a current to flow through a current path including an MTJ element or the other current path including the MTJ element in accordance with writing data to be written, thereby writing the write data into the MTJ element, a write completion detector which monitors the voltage at a first connection node or a second connection node in accordance with the write data after the writing of the write data into the MTJ element starts, detects the completion of writing of the write data based on the voltage at either node, and supplies a write completion signal indicating the completion of data write, and a write controller that terminates the writing of the write data into the MTJ element in response to the write completion signal supplied from the write completion detector.
    Type: Application
    Filed: March 24, 2015
    Publication date: December 21, 2017
    Inventors: Takahiro Hanyu, Daisuke Suzuki, Masanori Natsui, Akira Mochizuki, Hideo Ohno, Tetsuo Endoh
  • Patent number: 9536584
    Abstract: A nonvolatile logic gate device is configured to include a resistive network of a memory structure in which at least three nonvolatile resistive elements are connected, a reference resistive network as a reference resistance providing a tolerance of the memory structure to a resistance value of the resistive network of the memory structure, a writing part operable to selectively write or rewrite a value of each of the nonvolatile resistive elements in the resistive network into a maximum or a minimum corresponding to a logical value to be read when data are stored into the resistive network, and a logic circuit structure operable to use, as a logical value of the memory structure, a value obtained by comparison between the resistance value of the resistive network and the resistance value of the reference resistive network.
    Type: Grant
    Filed: May 15, 2013
    Date of Patent: January 3, 2017
    Assignees: NEC CORPORATION, TOHOKU UNIVERSITY
    Inventors: Ryusuke Nebashi, Noboru Sakimura, Yukihide Tsuji, Ayuka Tada, Tadahiko Sugibayashi, Takahiro Hanyu, Tetsuo Endoh, Hideo Ohno
  • Patent number: 9466363
    Abstract: An integrated circuit that does not involve increase in power consumption or decrease in switching probability during a write operation that occur when a latch circuit using STT-MTJ device, etc. of the prior art is operated at high speed is provided. The integrated circuit 1 includes: a memory element 1B where write occurs when a specified period ? has elapsed after a write signal is input; and a basic circuit element 1A, which is an elementary device constituting a circuit and has a data retaining function, and characterized in that an operation frequency f1 in a first operation mode in the process of memory access of the basic circuit element 1A satisfies the following relation: ?>?1/f1(0<?1?1).
    Type: Grant
    Filed: December 4, 2012
    Date of Patent: October 11, 2016
    Assignee: TOHOKU UNIVERSITY
    Inventors: Tetsuo Endoh, Takashi Ohsawa, Hiroki Koike, Takahiro Hanyu, Hideo Ohno
  • Patent number: 9324429
    Abstract: A semiconductor storage device 1 includes: an input controller (3); and a content-addressable memory block (2) connected to the input controller (3). Each word circuit (4) of the content-addressable memory block (2) includes: a k-bit 1st-stage sub word (4a) connected to search line 1 (SL1) of the input controller (3); and an (n-k)-bit 2nd-stage sub word (4b) connected to search line 2 (SL2) of the input controller (3). The k-bit 1st-stage sub word (4a) and the (n-k)-bit 2nd-stage sub word (4b) are separated by a segmentation circuit (5). When the 1st-stage sub word outputs a match signal, the match result is stored in the segmentation circuit (5), and a plurality of local match circuits within the 2nd-stage sub word (4b) are operated.
    Type: Grant
    Filed: May 3, 2013
    Date of Patent: April 26, 2016
    Assignee: TOHOKU UNIVERSITY
    Inventors: Takahiro Hanyu, Shoun Matsunaga, Naoya Onizawa, Vincent Gaudet
  • Patent number: 9299435
    Abstract: Provided is a nonvolatile content addressable memory. Each word circuit includes a plurality of segments having an order relation. Each of the segments includes one or more memory cells. Each of the memory cells includes a nonvolatile storage element. Each of the segments includes a power switch for turning on/off a power of a memory cell of the segment. During stand-by, all the power switches are turned off, and, in search operation, the power switch is turned on as necessary for each of the segments.
    Type: Grant
    Filed: August 1, 2013
    Date of Patent: March 29, 2016
    Assignees: NEC CORPORATION, TOHOKU UNIVERSITY
    Inventors: Noboru Sakimura, Ryusuke Nebashi, Tadahiko Sugibayashi, Shoun Matsunaga, Takahiro Hanyu, Hideo Ohno