Abstract: In a semiconductor device which outputs read-out data and a reference clock synchronized therewith for use in passing the data to other device, the generating timing of the reference clock and the generating timing of the data are compared by timing comparators 11A and 11B with first and second strobe pulses, and the logical values of the timing comparison result are compared by logic comparators 12A and 12B with first and second expected values. A logical condition decider 13 decides whether the combination of the logical comparison results satisfies a predetermined condition. When the predetermined condition is met, the decider 13 decides that the phase difference between the reference clock and the data is larger than a predetermined value, or that the duration of the data is longer than a predetermined time.

Abstract: In a semiconductor device which outputs read-out data and a reference clock synchronized therewith for use in passing the data to other device, the generating timing of the reference clock and the generating timing of the data are compared by timing comparators 11A and 11B with first and second strobe pulses, and the logical values of the timing comparison result are compared by logic comparators 12A and 12B with first and second expected values. A logical condition decider 13 decides whether the combination of the logical comparison results satisfies a predetermined condition. When the predetermined condition is met, the decider 13 decides that the phase difference between the reference clock and the data is larger than a predetermined value, or that the duration of the data is longer than a predetermined time.

Abstract: A semiconductor test system makes possible to test memory devices having arbitrary latency cycles when using a plurality of pattern generators. In each of the pattern generators, a fixed cycle shift circuit shifts an expected value signal by one cycle with the operating period of the pattern generator, a selector selects one of the expected value signals from the plurality of pattern generators including the pattern generator of itself, and cycle shift circuit is provided at the output of the selector. In another aspect, the semiconductor test system further includes a plurality of timing generators for generating a plurality of strobe signals to be supplied to a comparator, and a plurality of phase converters for shifting the phases of the expected value pattern from the pattern generators.

Abstract: A semiconductor test system is to realize a pattern generation that makes possible to test memory devices having arbitrary cycle latency operations when using multiple pattern generators. A cycle shift circuit that outputs a delayed expected value signal by shifting the expected value by one cycle with the operating period of the pattern generator is arranged. A N to 1 selector that selects an arbitrary signal from the expected value signal output by the multiple pattern generators including itself and the delayed expected value signal output by the multiple pattern generators excluding itself is arranged. A cycle shift section is arranged for the output selected by the selector. An arbitrary cycle shift can be generated by the expected value pattern using the above multiple pattern generators.

Abstract: A plurality of clock signals, which determine the edge timing of a driver output waveform, are generated by a timing generator. Pattern data and control data synchronized therewith from selecting a waveform mode in real time are generated by a patter generator. An enable data generator generates enable data which determines whether to use A, B and C clock signals ACK, BCK and CCK which determine the edge timing of the driver output waveform, on the basis of a selected one of a plurality of waveform modes stored in a storage and the pattern data. A waveform generator generates the driver output waveform on the basis of the enable data and the A, B, and C clock signals which determine the edge timing of the driver output waveform.