Abstract: A semiconductor device including a semiconductor device package providing a capacitor in its circuit board and a semiconductor chip mounted on that package, wherein the capacitor is provided directly under a semiconductor chip mounting surface of the circuit board on which the semiconductor chip is to be mounted and the conductor circuit electrically connecting the semiconductor chip and capacitor is made the shortest distance by having the external connection terminals of the capacitor directly connected to the other surface of the connection pads exposed at one surface at the semiconductor chip mounting surface of the circuit board and to which the electrode terminals of the semiconductor chip are to be directly connected.

Abstract: A semiconductor device comprises a semiconductor element having an electrode forming surface on which an electrode terminal is formed, an insulating layer made of phenol resin covering the electrode forming surface, and a rewiring pattern connected at one thereof to the electrode terminal and at the other end thereof to an external connecting terminal. During a process for manufacturing the phenol resin is cured at a temperature of 180° C. to 200° C. to form the insulating layer.

Abstract: A semiconductor package of superior high frequency characteristics enabling easy mounting of a large-sized capacitor and thereby enabling fluctuation of the power supply voltage to be suppressed and enabling a reduction of the inductance of the wiring portion connecting the capacitor and a connection terminal, that is, a semiconductor package mounting a capacitor for suppressing fluctuation of a power supply voltage, wherein the capacitor is comprised of, in an attachment hole passing through the board in the thickness direction, a conductor wire to be connected to a connection terminal of a semiconductor chip at one end, a high dielectric constant material covering the conductor wire at a predetermined thickness, and a conductor layer arranged between the outer circumference of the high dielectric constant material and the inner wall of the attachment hole, provided as a coaxial structure having the conductor wire at its center, and a method of production of the same.

Abstract: A multilayer circuit board for mounting a semiconductor element thereon, comprising a core substrate of a metal material and a plurality of wiring layers stacked on either side of the core substrate, each of the stacked wiring layers being isolated from an adjacent wiring layer by an insulating layer interposed therebetween, the multilayer circuit board having an area at which a heat spreader for dissipating heat generated from the semiconductor element mounted on the circuit board is to be joined to the multilayer circuit board, wherein the multilayer circuit board allows the heat spreader to be joined to the core substrate without the insulating layers being interposed therebetween. A semiconductor device using the multilayer circuit board is also disclosed.

Abstract: A wiring layer for serving as a first electrode layer of a capacitor portion patterned in a predetermined shape on an insulative base member is formed. A resin layer for serving as a dielectric layer of the capacitor portion is formed on a surface of the wiring layer using an electrophoretic process. Another wiring layer for serving as a second electrode layer of the capacitor portion patterned in a predetermined shape by patterning on the insulative base member inclusive of the resin layer is formed.

Abstract: In a process of manufacturing a core substrate of a semiconductor package using a metal core, through holes are formed in required positions on the metal core by an etching or a punching. Then, surfaces of the metal core inclusive of inner walls of the through holes are filled with insulative resin by an electrophoretic deposition process so as to form resin films. Thereafter, conductive thin films are formed on the entire surfaces of the resin films and the insides of the through holes are filled with a conductive material.

Abstract: A process for making a multilayer wiring board includes the following steps of: laminating an electrically insulating resin substrate, having first and second surfaces and a metal layer formed on the first surface, onto a base material on which a predetermined wiring pattern is formed, so that the second surface of the resin substrate is adhered to the base material; removing a predetermined amount of the metal layer to form an opening at a position where a connection with the wiring pattern is to be provided; irradiating a laser beam toward the resin layer through the resin removed region to form a blind via hole having a diameter smaller than that of the opening, so that the wiring pattern is exposed at a bottom of the blind via hole; electroless plating to form an electroless plated film on the exposed wiring pattern, a side wall of the blind via hole, a step portion of the exposed resin layer, and at least a metal layer at a periphery of the opening; electro plating to form an electro plated film on the e

Abstract: A resin plate having wiring pattern recesses and via through holes is made. All of the surfaces of the resin plate including inner walls of said wiring pattern recesses and via through holes are coated with a metal film. An electroplating is applied using the metal film as a power-supply layer to fill a plated metal into the wiring pattern recesses and via through holes. The metal film formed on the resin plate except for the inner walls of the wiring pattern recesses and via through holes is removed, so that wiring pattern and via are exposed on a surface the same as that of the resin plate.

Abstract: A package for semiconductor devices, comprising a core board having a front side with a front side base wiring pattern formed thereon and a back side with a back side base wiring pattern formed thereon, the front and back side wiring patterns being electrically connected to each other through a conductor segment penetrating the core board; a front side laminate of upper wiring patterns with intermediate insulating layers intervening therebetween on the front side base wiring pattern, in which each adjacent pair of the upper wiring patterns are electrically connected to each other through a via plated coating on a side wall of viaholes penetrating one of the intermediate insulating layers that intervenes between the adjacent pair and in which an outermost one of the upper wiring patterns is patterned for electrical connection to a semiconductor chip; a back side laminate of insulating layers on the back side base wiring pattern; an external connection wiring pattern including external connection terminals on t

Abstract: A package for semiconductor devices, comprising a core board having a front side with a front side base wiring pattern formed thereon and a back side with a back side base wiring pattern formed thereon, the front and back side wiring patterns being electrically connected to each other through a conductor segment penetrating the core board; a front side laminate of upper wiring patterns with intermediate insulating layers intervening therebetween on the front side base wiring pattern, in which each adjacent pair of the upper wiring patterns are electrically connected to each other through a via plated coating on a side wall of viaholes penetrating one of the intermediate insulating layers that intervenes between the adjacent pair and in which an outermost one of the upper wiring patterns is patterned for electrical connection to a semiconductor chip; a back side laminate of insulating layers on the back side base wiring pattern; an external connection wiring pattern including external connection terminals on t

Abstract: An interconnection substrate comprises an uppermost interconnection layer having a plurality of terminal pads located at positions corresponding to a plurality of solder bumps (external connection terminals) provided on a semiconductor element which is to be mounted on the interconnection substrate. The interconnection substrate also has a metal column formed on each of the terminal pads and has a resin film covering a side surface of the metal column. The interconnection substrate further has an insulating layer formed on the uppermost interconnection layer so that a gap is formed between the insulating layer and an outer peripheral surface of the resin film.

Abstract: An alkaline developing solution for a radiation sensitive composition, which has no undissolved products even when the concentration of a pigment contained in a radiation sensitive composition is high, which does not cause such problems as scum, the residue after development and re-adhesion, and which can form pixels having a sharp pattern edge. The alkaline developing solution for a radiation sensitive composition is an aqueous solution which contains (A-1) at least one inorganic alkaline compound and (A-2) at least one organic alkaline compound selected from the group consisting of alkanolamines and alkylamines or which contains the above component (A-1), the above component (A-2) and (B) at least one nonionic surfactant selected from the group consisting of etherified polyoxyethylenes and etherified polyoxyethylene-polyoxypropylene block copolymers.

Abstract: A radiation sensitive composition comprising (A) a colorant, (B) an alkali-soluble resin, (C) a polyfunctional monomer and (D) a photopolymerization initiator. The alkali-soluble resin (B) is a copolymer of (1) a monomer represented by the following formula (1): wherein R.sup.1 is a hydrogen atom or a methyl group, and(2) an ethylenically unsaturated monomer having at least one carboxyl group in the molecule, and optionally (3) a copolymerizable ethylenically unsaturated monomer other than the above monomers (1) and (2). The radiation sensitive composition is useful for producing a color filter for transmission-type or reflection-type color liquid crystal display devices, etc.

Abstract: In a method for manufacturing a lead frame, a predetermined pattern is formed on a matrix 10 by a resist, an electro-deposition portion is provided in a cavity formed in the resist patterns 12, and the electrodeposition pattern 13 is separated from the matrix 10. The resist pattern is formed on the matrix 10 so that a cavity portion 17 connecting a plurality of cavity 16 ends for inner lead formation can be included in the resist pattern, and an electro-deposition portion is provided into the cavity portion 17 so that the electro-deposition pattern 13 can be formed into a configuration in which the tip ends of the inner leads 22 are connected by a connecting piece 21, and the electro-deposition pattern 13 is separated from the matrix 10 while the tip ends of the inner leads 22 are connected by the connecting piece 21.

Abstract: In a method for manufacturing a lead frame, a predetermined pattern is formed on a matrix 10 by a resist, an electro-deposition portion is provided in a cavity formed in the resist patterns 12, and the electro-deposition pattern 13 is separated from the matrix 10. The resist pattern is formed on the matrix 10 so that a cavity portion 17 connecting a plurality of cavity 16 ends for inner lead formation can be included in the resist pattern, and an electro-deposition portion is provided into the cavity portion 17 so that the electro-deposition pattern 13 can be formed into a configuration in which the tip ends of the inner leads 22 are connected by a connecting piece 21, and the electro-deposition pattern 13 is separated from the matrix 10 while the tip ends of the inner leads 22 are connected by the connecting piece 21.

Abstract: A method for manufacturing a lead frame employing a resist pattern formed on a matrix and having a cavity therein, in which an electro-deposition pattern is formed. A connecting cavity portion interconnects tip ends of inner lead cavity portions such that a connecting portion interconnects the tip ends of inner leads of the electro-deposition pattern formed in the cavity. The connecting piece is maintained while the electro-deposition pattern is separated from the matrix and the resist.

Abstract: The surface of an apparatus made of a Fe base alloy or Ni base alloy containing at least 35 wt. % of Cr is resistant to carbon deposition when the apparatus contacts carburizing/oxidizing atmospheres.