Abstract: A memory control device (20) includes an arbiter (21) that accepts an access request to a memory (10) including a plurality of bank groups each of which has a plurality of banks, and a memory controller (23) that issues a command corresponding to the access request accepted by the arbiter (21), and in a case where the arbiter (21) accepts an access request to a first bank group of the plurality of bank groups, the arbiter (21) suspends acceptance of another access request to the first bank group.

Abstract: A memory control circuit of the disclosure includes a memory control unit that controls a timing of command issuance to cause (tATP+tPTA) to be constant, where, in a memory having a plurality of banks, tATP is a period from issuance of a first ACT command to issuance of a PRE command that is directed a bank same as or different from a bank to which the first ACT command is issued, and tPTA is a period from the issuance of the PRE command to issuance of a second ACT command that is directed to a bank same as or different from the bank to which the PRE command is issued.

Abstract: A memory control circuit according to the disclosure includes a memory control section that selectively uses a first issuing mode in which a plurality of control commands are issued without performing bank group interleaving and a second issuing mode in which the bank group interleaving is performed and the plurality of control commands are issued, and thereby issues the control commands to a plurality of bank groups in a memory having a bank group function.

Abstract: The load on an arbiter that conducts arbitration among host devices is reduced in an information processing system that includes the host devices and a storage device. A memory management device includes detecting units and a command generating unit. Each of the detecting units detects a timing to execute a predetermined process for the storage device. The command generating unit generates a command common to the predetermined processes subjected to the detection in the detecting units, and a sideband signal unique to each of the predetermined signals having the execution timings detected.

Abstract: A memory control circuit according to the disclosure includes a memory control section that selectively uses a first issuing mode in which a plurality of control commands are issued without performing bank group interleaving and a second issuing mode in which the bank group interleaving is performed and the plurality of control commands are issued, and thereby issues the control commands to a plurality of bank groups in a memory having a bank group function.

Abstract: A memory control circuit of the disclosure includes a memory control unit that controls a timing of command issuance to cause (tATP+tPTA) to be constant, where, in a memory having a plurality of banks, tATP is a period from issuance of a first ACT command to issuance of a PRE command that is directed a bank same as or different from a bank to which the first ACT command is issued, and tPTA is a period from the issuance of the PRE command to issuance of a second ACT command that is directed to a bank same as or different from the bank to which the PRE command is issued.

Abstract: To shorten data reading time taken with respect to a memory. A selection unit selects, with respect to a first memory to which access is made in units of blocks that are recording areas divided by a block size constituted by a plurality of pieces of data and in which a plurality of pieces of recording data are recorded from the head of a recording start block, and a second memory to which access is made in units of the blocks and in which the plurality of pieces of recording data are recorded from the middle of the recording start block, one of the first memory and the second memory as a read target on the basis of the number of the blocks necessary for reading data included in the recording data recorded in the first memory or the second memory. A read control unit performs reading from one of the first memory and the second memory on the basis of a result of the selection.

Abstract: The load on an arbiter that conducts arbitration among host devices is reduced in an information processing system that includes the host devices and a storage device. A memory management device includes detecting units and a command generating unit. Each of the detecting units detects a timing to execute a predetermined process for the storage device. The command generating unit generates a command common to the predetermined processes subjected to the detection in the detecting units, and a sideband signal unique to each of the predetermined signals having the execution timings detected.

Abstract: A memory controlling device that includes a request generating section for generating a memory request, a row selecting information retaining section that retains data relative to row address information, a column selecting information retaining section that retains data relative to column address information, a memory bank information for managing section operation states of the memory device, a command generating section for generating operation commands, and a command aligning section that synchronizes the operation commands with the clock.

Abstract: Disclosed herein is a memory controlling device including: an address converting section configured to convert a logical address included in a request issued from a plurality of clients into a physical address of a memory; a request dividing section configured to divide a converted request converted by the address converting section by a command unit for the memory on a basis of the physical address of the converted request; and an arbitrating section configured to perform arbitration on a basis of the physical address indicated in a divided request output from the request dividing section.

Abstract: Disclosed herein is a memory controlling device including: an address converting section configured to convert a logical address included in a request issued from a plurality of clients into a physical address of a memory; a request dividing section configured to divide a converted request converted by the address converting section by a command unit for the memory on a basis of the physical address of the converted request; and an arbitrating section configured to perform arbitration on a basis of the physical address indicated in a divided request output from the request dividing section.

Abstract: A memory controlling device includes: a request generating section; a row selecting information retaining section; a column selecting information retaining section; a memory bank information managing section; a command generating section; and a command aligning section.