Patents by Inventor Takahiro Ikenobe

Takahiro Ikenobe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • High-speed data readable information processing device
    Patent number: 7613863
    Abstract: A CAN module receives a message from a CAN bus to store the same in a message box unit of a message box. A reception request signal is output from the message box unit to a DMAC/IF. The DMAC/IF outputs a 7-bit encoded address together with a transfer request signal. A DMAC accesses a selected message box unit of the CAN module and a memory based on the transfer request signal and the 7-bit encoded address to transfer the message stored in the selected message box unit to the memory.
    Type: Grant
    Filed: April 1, 2008
    Date of Patent: November 3, 2009
    Assignee: Renesas Technology Corporation
    Inventors: Hideo Inoue, Isao Minematsu, Takahiro Ikenobe
  • High-speed data readable information processing device
    Publication number: 20080256267
    Abstract: A CAN module receives a message from a CAN bus to store the same in a message box unit of a message box. A reception request signal is output from the message box unit to a DMAC/IF. The DMAC/IF outputs a 7-bit encoded address together with a transfer request signal. A DMAC accesses a selected message box unit of the CAN module and a memory based on the transfer request signal and the 7-bit encoded address to transfer the message stored in the selected message box unit to the memory.
    Type: Application
    Filed: April 1, 2008
    Publication date: October 16, 2008
    Applicant: RENESAS TECHNOLOGY CORP.
    Inventors: Hideo Inoue, Isao Minematsu, Takahiro Ikenobe
  • High-speed data readable information processing device
    Patent number: 7370131
    Abstract: A CAN module receives a message from a CAN bus to store the same in a message box unit of a message box. A reception request signal is output from the message box unit to a DMAC/IF. The DMAC/IF outputs a 7-bit encoded address together with a transfer request signal. A DMAC accesses a selected message box unit of the CAN module and a memory based on the transfer request signal and the 7-bit encoded address to transfer the message stored in the selected message box unit to the memory.
    Type: Grant
    Filed: April 20, 2006
    Date of Patent: May 6, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Hideo Inoue, Isao Minematsu, Takahiro Ikenobe
  • High-speed data readable information processing device
    Publication number: 20060242255
    Abstract: A CAN module receives a message from a CAN bus to store the same in a message box unit of a message box. A reception request signal is output from the message box unit to a DMAC/IF. The DMAC/IF outputs a 7-bit encoded address together with a transfer request signal. A DMAC accesses a selected message box unit of the CAN module and a memory based on the transfer request signal and the 7-bit encoded address to transfer the message stored in the selected message box unit to the memory.
    Type: Application
    Filed: April 20, 2006
    Publication date: October 26, 2006
    Inventors: Hideo Inoue, Isao Minematsu, Takahiro Ikenobe