Abstract: A vehicle body side part structure for a vehicle includes a side sill connected to the lower part of a pillar, and a partition member provided within the side sill. The partition member includes a partition wall for dividing a closed sectional space of the side sill in the vehicle front-rear direction, and joint flange joined to the inner surface of a side sill inner member. The partition wall includes a ridge extending from a side of the side sill outer reinforcement to a side of the side sill inner member and connected to the joint flange. A widening portion is formed at an end of on the ridge close to the joint flange. This configuration makes it possible to improve the load transmission performance at the time of a side collision of the vehicle.

Abstract: A Very Long Instruction Word (VLIW) processor having an instruction set with a reduced size resulting in a small number of bits being necessary to specify registers. The VLIW processor includes a register file, and first through third operation units, and executes a very long instruction word. Further, the very long instruction word includes a register specifying field which specifies a least one of the registers in the register file and a plurality of instructions. The operand of each instruction includes bits src1, src2, and dst, which indicate whether or not the registers specified by the register specifying field are to be used as the source register and the destination register.

Abstract: A vehicle body side part structure for a vehicle includes a side sill connected to the lower part of a pillar, and a partition member provided within the side sill. The partition member includes a partition wall for dividing a closed sectional space of the side sill in the vehicle front-rear direction, and joint flange joined to the inner surface of a side sill inner member. The partition wall includes a ridge extending from a side of the side sill outer reinforcement to a side of the side sill inner member and connected to the joint flange. A widening portion is formed at an end of on the ridge close to the joint flange. This configuration makes it possible to improve the load transmission performance at the time of a side collision of the vehicle.

Abstract: A Very Long Instruction Word (VLIW) processor having an instruction set with a reduced size resulting in a small number of bits being necessary to specify registers. The VLIW processor includes a register file, and first through third operation units, and executes a very long instruction word. Further, the very long instruction word includes a register specifying field which specifies a least one of the registers in the register file and a plurality of instructions. The operand of each instruction includes bits src1, src2, and dst, which indicate whether or not the registers specified by the register specifying field are to be used as the source register and the destination register.

Abstract: A Very Long Instruction Word (VLIW) processor having an instruction set with a reduced size resulting in a small number of bits being necessary to specify registers. The VLIW processor includes a register file, and first through third operation units, and executes a very long instruction word. Further, the very long instruction word includes a register specifying field which specifies a least one of the registers in the register file and a plurality of instructions. The operand of each instruction includes bits src1, src2, and dst, which indicate whether or not the registers specified by the register specifying field are to be used as the source register and the destination register.

Abstract: A variable-length code decoding apparatus that decodes a bitstream includes: a storage unit that stores a variable-length code table; a bitstream cutout unit that outputs a bit string of a fixed length; a reference unit that outputs decoded data and a code length with reference to the storage unit; a determination unit that determines whether a bit string of the fixed length is accumulated; a determination unit that determines whether a bit string of a length that is shorter than the fixed length is accumulated; and a selection unit that selects one of the determination results from the determination units. The bitstream cutout unit sets a starting bit based on the selected determination result, and the selection unit switches the selection of the determination results from the determination units.

Abstract: A variable-length code decoding apparatus that decodes a bitstream includes: a storage unit that stores a variable-length code table; a bitstream cutout unit that outputs a bit string of a fixed length; a reference unit that outputs decoded data and a code length with reference to the storage unit; a determination unit that determines whether a bit string of the fixed length is accumulated; a determination unit that determines whether a bit string of a length that is shorter than the fixed length is accumulated; and a selection unit that selects one of the determination results from the determination units. The bitstream cutout unit sets a starting bit based on the selected determination result, and the selection unit switches the selection of the determination results from the determination units.

Abstract: A Very Long Instruction Word (VLIW) processor having an instruction set with a reduced size resulting in a small number of bits being necessary to specify registers. The VLIW processor includes a register file, and first through third operation units, and executes a very long instruction word. Further, the very long instruction word includes a register specifying field which specifies a least one of the registers in the register file and a plurality of instructions. The operand of each instruction includes bits src1, src2, and dst, which indicate whether or not the registers specified by the register specifying field are to be used as the source register and the destination register.

Abstract: A Very Long Instruction Word (VLIW) processor having an instruction set with a reduced size resulting in a small number of bits being necessary to specify registers. The VLIW processor includes a register file, and first through third operation units, and executes a very long instruction word. Further, the very long instruction word includes a register specifying field which specifies a least one of the registers in the register file and a plurality of instructions. The operand of each instruction includes bits src1, src2, and dst, which indicate whether or not the registers specified by the register specifying field are to be used as the source register and the destination register.

Abstract: A VLIW processor which has an instruction set whose size is reduced so that a small number of bits are necessary to specify registers is provided. The VLIW processor 10 comprises the register file 12, the first-the third operation units 14a-14c and the like, and executes the very long instruction word. And, the very long instruction word includes the register specifying field which specifies a least one of the registers in the register file 12 and a plurality of instructions. The operand of each instruction has the bits, src1 src2 and dst, indicating whether or not the registers specified by the register specifying field are to be used as the source register and the destination register.