Abstract: A semiconductor device includes a control unit which controls charging/discharging of a secondary battery, a bidirectional coupling unit which is electrically coupled to the control unit and through which a charging/discharging current flows, and a protection diode coupled between the control unit and the bidirectional coupling unit. The bidirectional coupling unit includes a discharging power transistor, a charging power transistor reversely coupled in series with the discharging power transistor, and a common drain pad which functions as a drain of the discharging power transistor and further functions as a drain of the charging power transistor. An anode of the protection diode is electrically coupled to the common drain pad. A cathode of the protection diode is electrically coupled to a power supply terminal of the control unit.

Abstract: A semiconductor device capable of reducing an inter-source electrode resistance RSS (on) and reducing a chip size is provided. A semiconductor device according to the present invention includes a chip partitioned into three areas including a first area, a second area, and a third area, and a common drain electrode provided on a back surface of the chip, in which the second area is formed between the first and third areas, a first MOSFET is formed in the first area and the third area, and a second MOSFET is formed in the second area.

Abstract: A semiconductor device includes a control unit which controls charging/discharging of a secondary battery, a bidirectional coupling unit which is electrically coupled to the control unit and through which a charging/discharging current flows, and a protection diode coupled between the control unit and the bidirectional coupling unit. The bidirectional coupling unit includes a discharging power transistor, a charging power transistor reversely coupled in series with the discharging power transistor, and a common drain pad which functions as a drain of the discharging power transistor and further functions as a drain of the charging power transistor. An anode of the protection diode is electrically coupled to the common drain pad. A cathode of the protection diode is electrically coupled to a power supply terminal of the control unit.

Abstract: A method of manufacturing a semiconductor apparatus includes setting first and second areas on a semiconductor chip, forming a first transistor in the first area, forming a second transistor in the second area, and forming a gate pad of a first transistor and a gate pad of a second transistor in the second area.

Abstract: To provide a semiconductor product high in versatility. A common drain pad is formed over the surface of a semiconductor chip together with source pads and gate pads of discharging and charging power transistors. Thus, when the semiconductor chip is face-down mounted over a wiring board, not only the source pads and gate pads of the discharging and charging power transistors, but also the common drain pad is electrically coupled to wirings of the wiring board.

Abstract: A semiconductor apparatus includes a first area, a first transistor being formed in two or more divided areas of the first area, and a second area, a second transistor being formed in two or more divided areas of the second area. The number of areas of the second area is greater than the number of areas of the first area, the divided areas of the first area and the second area are alternately arranged, and the gate pad of the first transistor and the gate pad of the second transistor are formed in the second area.

Abstract: A semiconductor device capable of reducing an inter-source electrode resistance RSS (on) and reducing a chip size is provided. A semiconductor device according to the present invention includes a chip partitioned into three areas including a first area, a second area, and a third area, and a common drain electrode provided on a back surface of the chip, in which the second area is formed between the first and third areas, a first MOSFET is formed in the first area and the third area, and a second MOSFET is formed in the second area.

Abstract: A semiconductor device capable of reducing an inter-source electrode resistance RSS(on) and reducing a chip size is provided. A semiconductor device according to the present invention includes a chip partitioned into three areas including a first area, a second area, and a third area, and a common drain electrode provided on a back surface of the chip, in which the second area is formed between the first and third areas, a first MOSFET is formed in the first area and the third area, and a second MOSFET is formed in the second area.

Abstract: To provide a semiconductor product high in versatility. A common drain pad is formed over the surface of a semiconductor chip together with source pads and gate pads of discharging and charging power transistors. Thus, when the semiconductor chip is face-down mounted over a wiring board, not only the source pads and gate pads of the discharging and charging power transistors, but also the common drain pad is electrically coupled to wirings of the wiring board.

Abstract: A semiconductor device including an active cell region formed over the surface of a silicon substrate and including a vertical MOSFET, a drain electrode formed over the surface of the silicon substrate and leading out the drain of the vertical MOSFET from the back surface of the silicon substrate, an external drain terminal formed over the drain electrode, and a source electrode formed over the active cell region so as to be opposed to the drain electrode at least along three sides at the periphery of the external drain terminal over the active cell region and connected to the source of the vertical MOSFET.

Abstract: A semiconductor apparatus includes a first area, a first transistor being formed in two or more divided areas of the first area, and a second area, a second transistor being formed in two or more divided areas of the second area. The number of areas of the second area is greater than the number of areas of the first area, the divided areas of the first area and the second area are alternately arranged, and the gate pad of the first transistor and the gate pad of the second transistor are formed in the second area.

Abstract: According to one embodiment, a semiconductor apparatus divides each of a first area in which a first transistor is formed and a second area in which a second transistor is formed into two or more areas, and alternately arranges the divided areas of the first area and the second area. Further, the semiconductor apparatus according to one embodiment configures the second area to have a total area larger than that of the first area or to have the number of divisions greater than that of the first area. Furthermore, in the semiconductor apparatus according to one embodiment, a gate pad of the first transistor and a gate pad of the second transistor are provided in the second area.

Abstract: A semiconductor device capable of reducing an inter-source electrode resistance RSS(on) and reducing a chip size is provided. A semiconductor device according to the present invention includes a chip partitioned into three areas including a first area, a second area, and a third area, and a common drain electrode provided on a back surface of the chip, in which the second area is formed between the first and third areas, a first MOSFET is formed in the first area and the third area, and a second MOSFET is formed in the second area.

Abstract: A semiconductor device capable of reducing an inter-source electrode resistance RSS(on) and reducing a chip size is provided. A semiconductor device according to the present invention includes a chip partitioned into three areas including a first area, a second area, and a third area, and a common drain electrode provided on a back surface of the chip, in which the second area is formed between the first and third areas, a first MOSFET is formed in the first area and the third area, and a second MOSFET is formed in the second area.

Abstract: According to one embodiment, a semiconductor apparatus divides each of a first area in which a first transistor is formed and a second area in which a second transistor is formed into two or more areas, and alternately arranges the divided areas of the first area and the second area. Further, the semiconductor apparatus according to one embodiment configures the second area to have a total area larger than that of the first area or to have the number of divisions greater than that of the first area. Furthermore, in the semiconductor apparatus according to one embodiment, a gate pad of the first transistor and a gate pad of the second transistor are provided in the second area.

Abstract: A semiconductor device including an active cell region formed over the surface of a silicon substrate and including a vertical MOSFET, a drain electrode formed over the surface of the silicon substrate and leading out the drain of the vertical MOSFET from the back surface of the silicon substrate, an external drain terminal formed over the drain electrode, and a source electrode formed over the active cell region so as to be opposed to the drain electrode at least along three sides at the periphery of the external drain terminal over the active cell region and connected to the source of the vertical MOSFET.

Abstract: The present invention provides a thin-film transistor manufactured on a transparent substrate having a structure of a top gate type crystalline silicon thin-film transistor in which a light blocking film, a base layer, a crystalline silicon film, a gate insulating film, and a gate electrode film arranged not to overlap at least a channel region are sequentially formed on the transparent substrate; wherein the channel region having channel length L, LDD regions having LDD length d on both sides of the channel region, a source region, and a drain region are formed in the crystalline silicon film; the light blocking film is divided across the channel region; and interval x between the divided light blocking films is equal to or larger than channel length L and equal to or smaller than a sum of channel length L and a double of LDD length d (L+2d). Thereby, the cost for manufacturing the thin-film transistor is low, and the photo leak current of the thin-film transistor is suppressed.

Abstract: A device excellent in electrical characteristics is provided by suppressing an operation failure owing to a hysteresis effect that occurs in a circuit using MOS transistors having floating bodies. Moreover, sensitivity of a sense amplifier circuit and a latch circuit including these MOS transistors as components is improved. A signal required in a circuit other than a first circuit is outputted by using electrical characteristics of MOS transistors in a first period (effective period), and in a second period (idle period) excluding the first period, between the gate and source of MOS transistors, a step waveform voltage not less than threshold voltages of these MOS transistors is given.

Abstract: A semiconductor device capable of reducing an inter-source electrode resistance RSS(on) and reducing a chip size is provided. A semiconductor device according to the present invention includes a chip partitioned into three areas including a first area, a second area, and a third area, and a common drain electrode provided on a back surface of the chip, in which the second area is formed between the first and third areas, a first MOSFET is formed in the first area and the third area, and a second MOSFET is formed in the second area.

Abstract: Off-leak current of a TFT, required for a drive circuit configured with a TFT of a single conductivity type, is realized with simple manufacturing steps. The impurity concentration of a source region and a drain region of a TFT is set between 2*1018 cm?3 and 2*1019 cm?3, whereby off-leak current of the TFT can be sufficiently reduced even in a single gate structure.