Patents by Inventor Takahiro Kumauchi
Takahiro Kumauchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140030865Abstract: To provide a semiconductor device including: plural capacitors each including a cylindrical lower electrode having an internal wall and an external wall, and an upper electrode that covers the external wall of the lower electrode via a capacitance dielectric film; and a supporting film having a buried portion buried in an internal region surrounded by the internal wall of the lower electrode, and a supporting portion a part of which is positioned within the internal region and remaining parts of which are positioned at outside of the internal region. The supporting portion sandwiches an upper end of the lower electrode at both ends of the upper end by covering the internal wall and the external wall of the upper end of the lower electrode.Type: ApplicationFiled: September 30, 2013Publication date: January 30, 2014Applicant: Elpida Memory, Inc.Inventors: Satoru ISOGAI, Takahiro KUMAUCHI
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Patent number: 8581315Abstract: To provide a semiconductor device including: plural capacitors each including a cylindrical lower electrode having an internal wall and an external wall, and an upper electrode that covers the external wall of the lower electrode via a capacitance dielectric film; and a supporting film having a buried portion buried in an internal region surrounded by the internal wall of the lower electrode, and a supporting portion a part of which is positioned within the internal region and remaining parts of which are positioned at outside of the internal region. The supporting portion sandwiches an upper end of the lower electrode at both ends of the upper end by covering the internal wall and the external wall of the upper end of the lower electrode.Type: GrantFiled: February 6, 2012Date of Patent: November 12, 2013Assignee: Elpida Memory, Inc.Inventors: Satoru Isogai, Takahiro Kumauchi
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Publication number: 20130032924Abstract: To provide a semiconductor device including: plural capacitors each including a cylindrical lower electrode having an internal wall and an external wall, and an upper electrode that covers the external wall of the lower electrode via a capacitance dielectric film; and a supporting film having a buried portion buried in an internal region surrounded by the internal wall of the lower electrode, and a supporting portion a part of which is positioned within the internal region and remaining parts of which are positioned at outside of the internal region. The supporting portion sandwiches an upper end of the lower electrode at both ends of the upper end by covering the internal wall and the external wall of the upper end of the lower electrode.Type: ApplicationFiled: February 6, 2012Publication date: February 7, 2013Applicant: ELPIDA MEMORY, INC.Inventors: SATORU ISOGAI, TAKAHIRO KUMAUCHI
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Patent number: 8138536Abstract: To provide a semiconductor device including: plural capacitors each including a cylindrical lower electrode having an internal wall and an external wall, and an upper electrode that covers the external wall of the lower electrode via a capacitance dielectric film; and a supporting film having a buried portion buried in an internal region surrounded by the internal wall of the lower electrode, and a supporting portion a part of which is positioned within the internal region and remaining parts of which are positioned at outside of the internal region. The supporting portion sandwiches an upper end of the lower electrode at both ends of the upper end by covering the internal wall and the external wall of the upper end of the lower electrode.Type: GrantFiled: December 24, 2009Date of Patent: March 20, 2012Assignee: Elpida Memory, Inc.Inventors: Satoru Isogai, Takahiro Kumauchi
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Publication number: 20100155891Abstract: To provide a semiconductor device including: plural capacitors each including a cylindrical lower electrode having an internal wall and an external wall, and an upper electrode that covers the external wall of the lower electrode via a capacitance dielectric film; and a supporting film having a buried portion buried in an internal region surrounded by the internal wall of the lower electrode, and a supporting portion a part of which is positioned within the internal region and remaining parts of which are positioned at outside of the internal region. The supporting portion sandwiches an upper end of the lower electrode at both ends of the upper end by covering the internal wall and the external wall of the upper end of the lower electrode.Type: ApplicationFiled: December 24, 2009Publication date: June 24, 2010Applicant: ELPIDA MEMORY, INC.Inventors: Satoru ISOGAI, Takahiro KUMAUCHI
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Patent number: 7687849Abstract: Disclosed is a technique for reducing the leak current by reducing contamination of metal composing a polymetal gate of a MISFET. Of a polycrystalline silicon film, a WN film, a W film, and a cap insulating film formed on a gate insulating film on a p-type well (semiconductor substrate), the cap insulating film, the W film, and the WN film are etched and the over-etching of the polycrystalline silicon film below them is performed. Then, a sidewall film is formed on sidewalls of these films. Thereafter, after etching the polycrystalline silicon film with using the sidewall film as a mask, a thermal treatment is performed in an oxidation atmosphere, by which a light oxide film is formed on the sidewall of the polycrystalline silicon film. As a result, the contamination on the gate insulating film due to the W and the W oxide can be reduced, and also, the diffusion of these materials into the semiconductor substrate (p-type well) and the resultant increase of the leak current can be prevented.Type: GrantFiled: May 29, 2008Date of Patent: March 30, 2010Assignee: Elpida Memory, Inc.Inventors: Hiroshi Kujirai, Kousuke Okuyama, Kazuhiro Hata, Kiyonori Oyu, Ryo Nagai, Hiroyuki Uchiyama, Takahiro Kumauchi, Teruhisa Ichise
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Publication number: 20080237752Abstract: Disclosed is a technique for reducing the leak current by reducing contamination of metal composing a polymetal gate of a MISFET. Of a polycrystalline silicon film, a WN film, a W film, and a cap insulating film formed on a gate insulating film on a p-type well (semiconductor substrate), the cap insulating film, the W film, and the WN film are etched and the over-etching of the polycrystalline silicon film below them is performed. Then, a sidewall film is formed on sidewalls of these films. Thereafter, after etching the polycrystalline silicon film with using the sidewall film as a mask, a thermal treatment is performed in an oxidation atmosphere, by which a light oxide film is formed on the sidewall of the polycrystalline silicon film. As a result, the contamination on the gate insulating film due to the W and the W oxide can be reduced, and also, the diffusion of these materials into the semiconductor substrate (p-type well) and the resultant increase of the leak current can be prevented.Type: ApplicationFiled: May 29, 2008Publication date: October 2, 2008Inventors: Hiroshi Kujirai, Kousuke Okuyama, Kazuhiro Hata, Kiyonori Oyu, Ryo Nagai, Hiroyuki Uchiyama, Takahiro Kumauchi, Teruhisa Ichise
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Patent number: 7417291Abstract: Disclosed is a technique for reducing the leak current by reducing contamination of metal composing a polymetal gate of a MISFET. Of a polycrystalline silicon film, a WN film, a W film, and a cap insulating film formed on a gate insulating film on a p-type well (semiconductor substrate), the cap insulating film, the W film, and the WN film are etched and the over-etching of the polycrystalline silicon film below them is performed. Then, a sidewall film is formed on sidewalls of these films. Thereafter, after etching the polycrystalline silicon film with using the sidewall film as a mask, a thermal treatment is performed in an oxidation atmosphere, by which a light oxide film is formed on the sidewall of the polycrystalline silicon film. As a result, the contamination on the gate insulating film due to the W and the W oxide can be reduced, and also, the diffusion of these materials into the semiconductor substrate (p-type well) and the resultant increase of the leak current can be prevented.Type: GrantFiled: April 18, 2007Date of Patent: August 26, 2008Assignee: Elpida Memory, Inc.Inventors: Hiroshi Kujirai, Kousuke Okuyama, Kazuhiro Hata, Kiyonori Oyu, Ryo Nagai, Hiroyuki Uchiyama, Takahiro Kumauchi, Teruhisa Ichise
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Publication number: 20070187783Abstract: Disclosed is a technique for reducing the leak current by reducing contamination of metal composing a polymetal gate of a MISFET. Of a polycrystalline silicon film, a WN film, a W film, and a cap insulating film formed on a gate insulating film on a p-type well (semiconductor substrate), the cap insulating film, the W film, and the WN film are etched and the over-etching of the polycrystalline silicon film below them is performed. Then, a sidewall film is formed on sidewalls of these films. Thereafter, after etching the polycrystalline silicon film with using the sidewall film as a mask, a thermal treatment is performed in an oxidation atmosphere, by which a light oxide film is formed on the sidewall of the polycrystalline silicon film. As a result, the contamination on the gate insulating film due to the W and the W oxide can be reduced, and also, the diffusion of these materials into the semiconductor substrate (p-type well) and the resultant increase of the leak current can be prevented.Type: ApplicationFiled: April 18, 2007Publication date: August 16, 2007Inventors: Hiroshi Kujirai, Kousuke Okuyama, Kazuhiro Hata, Kiyonori Oyu, Ryo Nagai, Hiroyuki Uchiyama, Takahiro Kumauchi, Teruhisa Ichise
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Patent number: 7224034Abstract: Disclosed is a technique for reducing the leak current by reducing contamination of metal composing a polymetal gate of a MISFET: Of a polycrystalline silicon film, a WN film, a W film, and a cap insulating film formed on a gate insulating film on a p-type well (semiconductor substrate), the cap insulating film, the W film, and the WN film are etched and the over-etching of the polycrystalline silicon film below them is performed. Then, a sidewall film is formed on sidewalls of these films. Thereafter, after etching the polycrystalline silicon film with using the sidewall film as a mask, a thermal treatment is performed in an oxidation atmosphere, by which a light oxide film is formed on the sidewall of the polycrystalline silicon film. As a result, the contamination on the gate insulating film due to the W and the W oxide can be reduced, and also, the diffusion of these materials into the semiconductor substrate (p-type well) and the resultant increase of the leak current can be prevented.Type: GrantFiled: November 2, 2004Date of Patent: May 29, 2007Assignee: Elpida Memory, Inc.Inventors: Hiroshi Kujirai, Kousuke Okuyama, Kazuhiro Hata, Kiyonori Oyu, Ryo Nagai, Hiroyuki Uchiyama, Takahiro Kumauchi, Teruhisa Ichise
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Patent number: 7042038Abstract: An active region (L) with a metal insulator semiconductor field effect transistor (MISFET) (Qs) formed therein for selection of a DRAM memory cell, which makes up a memory cell of the DRAM, is arranged to have an island-like pattern that linearly extends in an X direction on one principal surface of a semiconductor substrate (1). The memory-cell selection MISFET (Qs) has an insulated gate electrode (7) (word line WL) that extends along a Y direction on the principal surface of the semiconductor substrate (1) with the same width kept along the length thereof, which gate electrode is arranged to oppose another gate electrode (7) (word line WL) adjacent thereto at a prespecified distance or pitch that is narrower than said width.Type: GrantFiled: September 4, 2003Date of Patent: May 9, 2006Assignee: Hitachi, Ltd.Inventors: Makoto Yoshida, Takahiro Kumauchi, Yoshitaka Tadaki, Isamu Asano, Norio Hasegawa, Keizo Kawakita
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Publication number: 20060024875Abstract: In a process for manufacturing a semiconductor integrated circuit device having a MISFET, in order that a shallow junction between the source/drain of the MISFET and a semiconductor substrate may be realized by reducing the number of heat treatment steps, all conductive films to be deposited on the semiconductor substrate are deposited at a temperature of 500° C. or lower at a step after the MISFET has been formed. Moreover, all insulating films to be deposited over the semiconductor substrate are deposited at a temperature of 500° C. or lower at a step after the MISFET has been formed.Type: ApplicationFiled: September 26, 2005Publication date: February 2, 2006Inventors: Makoto Yoshida, Takahiro Kumauchi, Yoshitaka Tadaki, Kazuhiko Kajigaya, Hideo Aoki, Isamu Asano
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Publication number: 20050087880Abstract: Disclosed is a technique for reducing the leak current by reducing contamination of metal composing a polymetal gate of a MISFET: Of a polycrystalline silicon film, a WN film, a W film, and a cap insulating film formed on a gate insulating film on a p-type well (semiconductor substrate), the cap insulating film, the W film, and the WN film are etched and the over-etching of the polycrystalline silicon film below them is performed. Then, a sidewall film is formed on sidewalls of these films. Thereafter, after etching the polycrystalline silicon film with using the sidewall film as a mask, a thermal treatment is performed in an oxidation atmosphere, by which a light oxide film is formed on the sidewall of the polycrystalline silicon film. As a result, the contamination on the gate insulating film due to the W and the W oxide can be reduced, and also, the diffusion of these materials into the semiconductor substrate (p-type well) and the resultant increase of the leak current can be prevented.Type: ApplicationFiled: November 2, 2004Publication date: April 28, 2005Inventors: Hiroshi Kujirai, Kousuke Okuyama, Kazuhiro Hata, Kiyonori Oyu, Ryo Nagai, Hiroyuki Uchiyama, Takahiro Kumauchi, Teruhisa Ichise
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Publication number: 20050042822Abstract: In a process for manufacturing a semiconductor integrated circuit device having a MISFET, in order that a shallow junction between the source/drain of the MISFET and a semiconductor substrate may be realized by reducing the number of heat treatment steps, all conductive films to be deposited on the semiconductor substrate are deposited at a temperature of 500° C. or lower at a step after the MISFET has been formed. Moreover, all insulating films to be deposited over the semiconductor substrate are deposited at a temperature of 500° C. or lower at a step after the MISFET has been formed.Type: ApplicationFiled: September 28, 2004Publication date: February 24, 2005Inventors: Makoto Yoshida, Takahiro Kumauchi, Yoshitaka Tadaki, Kazuhiko Kajigaya, Hideo Aoki, Isamu Asano
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Patent number: 6852579Abstract: Oxidation on the surface of a film of refractory metal constituting a gate electrode (word line WL) is suppressed by forming an insulation film constituting a cap insulation film of the gate electrode (word line WL) at a temperature of 500° C. or lower. Further, oxidation on the surface of the refractory metal film exposed to the side wall of the gate electrode (word line WL) is suppressed by forming an insulation film constituting the side wall spacer of the gate electrode (word line WL) at a temperature of 500° C. or lower.Type: GrantFiled: February 13, 2003Date of Patent: February 8, 2005Assignee: Hitachi, Ltd.Inventors: Takahiro Kumauchi, Makoto Yoshida, Kazuhiko Kajigaya
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Patent number: 6828242Abstract: Disclosed is a technique for reducing the leak current by reducing contamination of metal composing a polymetal gate of a MISFET. Of a polycrystalline silicon film, a WN film, a W film, and a cap insulating film formed on a gate insulating film on a p-type well (semiconductor substrate), the cap insulating film, the W film, and the WN film are etched and the over-etching of the polycrystalline silicon film below them is performed. Then, a sidewall film is formed on sidewalls of these films. Thereafter, after etching the polycrystalline silicon film with using the sidewall film as a mask, a thermal treatment is performed in an oxidation atmosphere, by which a light oxide film is formed on the sidewall of the polycrystalline silicon film. As a result, the contamination on the gate insulating film due to the W and the W oxide can be reduced, and also, the diffusion of these materials into the semiconductor substrate (p-type well) and the resultant increase of the leak current can be prevented.Type: GrantFiled: August 20, 2002Date of Patent: December 7, 2004Assignees: Hitachi, Ltd., NEC Corporation, NEC Electronics CorporationInventors: Hiroshi Kujirai, Kousuke Okuyama, Kazuhiro Hata, Kiyonori Oyu, Ryo Nagai, Hiroyuki Uchiyama, Takahiro Kumauchi, Teruhisa Ichise
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Patent number: 6815762Abstract: In a process for manufacturing a semiconductor integrated circuit device having a MISFET, in order that a shallow junction between the source/drain of the MISFET and a semiconductor substrate may be realized by reducing the number of heat treatment steps, all conductive films to be deposited on the semiconductor substrate are deposited at a temperature of 500° C. or lower at a step after the MISFET has been formed. Moreover, all insulating films to be deposited over the semiconductor substrate are deposited at a temperature of 500° C. or lower at a step after the MISFET has been formed.Type: GrantFiled: October 13, 1999Date of Patent: November 9, 2004Assignee: Hitachi, Ltd.Inventors: Makoto Yoshida, Takahiro Kumauchi, Yoshitaka Tadaki, Kazuhiko Kajigaya, Hideo Aoki, Isamu Asano
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Publication number: 20040043546Abstract: An active region (L) with a metal insulator semiconductor field effect transistor (MISFET) (Qs) formed therein for selection of a DRAM memory cell, which makes up a memory cell of the DRAM, is arranged to have an island-like pattern that linearly extends in an X direction on one principal surface of a semiconductor substrate (1). The memory-cell selection MISFET (Qs) has an insulated gate electrode (7) (word line WL) that extends along a Y direction on the principal surface of the semiconductor substrate (1) with the same width kept along the length thereof, which gate electrode is arranged to oppose another gate electrode (7) (word line WL) adjacent thereto at a prespecified distance or pitch that is narrower than said width.Type: ApplicationFiled: September 4, 2003Publication date: March 4, 2004Inventors: Makoto Yoshida, Takahiro Kumauchi, Yoshitaka Tadaki, Isamu Asano, Norio Hasegawa, Keizo Kawakita
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Patent number: 6649956Abstract: An active region (L) with a metal insulator semiconductor field effect transistor (MISFET) (Qs) formed therein for selection of a DRAM memory cell, which makes up a memory cell of the DRAM, is arranged to have an island-like pattern that linearly extends in an X direction on one principal surface of a semiconductor substrate (1). The memory-cell selection MISFET (Qs) has an insulated gate electrode (7) (word line WL) that extends along a Y direction on the principal surface of the semiconductor substrate (1) with the same width kept along the length thereof, which gate electrode is arranged to oppose another gate electrode (7) (word line WL) adjacent thereto at a prespecified distance or pitch that is narrower than said width.Type: GrantFiled: August 27, 2002Date of Patent: November 18, 2003Assignee: Hitachi, Ltd.Inventors: Makoto Yoshida, Takahiro Kumauchi, Yoshitaka Tadaki, Isamu Asano, Norio Hasegawa, Keizo Kawakita
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Publication number: 20030157757Abstract: Oxidation on the surface of a film of refractory metal constituting a gate electrode (word line WL) is suppressed by forming an insulation film constituting a cap insulation film of the gate electrode (word line WL) at a temperature of 500° C. or lower. Further, oxidation on the surface of the refractory metal film exposed to the side wall of the gate electrode (word line WL) is suppressed by forming an insulation film constituting the side wall spacer of the gate electrode (word line WL) at a temperature of 500° C. or lower.Type: ApplicationFiled: February 13, 2003Publication date: August 21, 2003Inventors: Takahiro Kumauchi, Makoto Yoshida, Kazuhiko Kajigaya