Patents by Inventor Takahiro Minaki

Takahiro Minaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230169167
    Abstract: A semiconductor device provides a method to avoid side-channel attacks. While the logic circuit A for performing the encryption process does not operate, by operating the logic circuit B (performing processing other than the encryption) having a circuit scale of approximately the same as the logic circuit A, the change in the consumption current interlocked with the operation state of the logic circuit A is shielded, it is possible to make it difficult to decrypt the encryption key of the logic circuit A by analyzing the current waveform.
    Type: Application
    Filed: October 3, 2022
    Publication date: June 1, 2023
    Inventor: Takahiro MINAKI
  • Patent number: 8593200
    Abstract: A clock generator includes a counter unit receiving a reference clock signal to generate a timing signal, a selector receiving the timing signal to output a clock enable based on bit string data stored in a storage unit and a clock gate cell receiving the reference clock signal based on the clock, thinning some pulses out from the reference clock signal based on the clock enable so that a clock signal is maskable, and outputting an inter intermittent clock signal.
    Type: Grant
    Filed: February 21, 2013
    Date of Patent: November 26, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Takahiro Minaki
  • Patent number: 8400202
    Abstract: A clock generator includes a counter receiving a reference clock signal to generate a timing signal based on the reference clock signal, and a plurality of intermittent clock generating units each coupled to a storage unit thereof storing a bit strings data, each of the intermittent clock generating units receiving the reference clock signal and the timing signal. Each of the intermittent clock generating units masks a clock pulse of the reference clock signal based on the bit string data stored in the storage unit thereof to output an intermittent clock signal in response to the timing signal.
    Type: Grant
    Filed: April 1, 2011
    Date of Patent: March 19, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Takahiro Minaki
  • Publication number: 20110248762
    Abstract: To provide a clock generator capable of suppressing a peak power, the circuit includes a counter receiving a reference clock signal to generate a timing signal based on the reference clock signal; and a plurality of intermittent clock generating units each coupled to a storage unit thereof storing a bit strings data, each of the intermittent clock generating units receiving the reference clock signal and the timing signal. Each of the intermittent clock generating units masks a clock pulse of the reference clock signal based on the bit string data stored in the storage unit thereof to output an intermittent clock signal in response to the timing signal.
    Type: Application
    Filed: April 1, 2011
    Publication date: October 13, 2011
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventor: Takahiro Minaki