Abstract: On the same semiconductor substrate 1, a memory cell array in which a plurality of memory elements R having a chalcogenide-material storage layer 22 storing a high-resistance state with a high electric resistance value and a low-resistance state with a low electric resistance value by a change of an atom arrangement are disposed in a matrix is formed in a memory cell region mmry, and a semiconductor integrated circuit is formed in a logic circuit region lgc. This chalcogenide-material storage layer 22 is made of a chalcogenide material containing at least either one of Ga or In of 10.5 atom % or larger to 40 atom % or smaller, Ge of 5 atom % or larger to 35 atom % or smaller, Sb of 5 atom % or larger to 25 atom % or smaller, and Te of 40 atom % or larger to 65 atom % or smaller.

Abstract: The annealing process at 400° C. or more required for the wiring process for a phase change memory has posed the problem in that the crystal grains in a chalcogenide material grow in an oblique direction to cause voids in a storage layer. The voids, in turn, cause peeling due to a decrease in adhesion, variations in resistance due to improper contact with a plug, and other undesirable events. After the chalcogenide material has been formed in an amorphous phase, post-annealing is conducted to form a (111)-oriented and columnarly structured face-centered cubic. This is further followed by high-temperature annealing to form a columnar, hexagonal closest-packed crystal. Use of this procedure makes it possible to suppress the growth of inclined crystal grains that causes voids, since crystal grains are formed in a direction perpendicular to the surface of an associated substrate.

Abstract: In a computer system comprising first through N-th processors which are provided with first through N-th processor input/output information transmission paths, respectively, an n-th processor is connected to an (n-1)-th processor, an (n-2)-th processor, an (n+1)-th processor, and an (n+2)-th processor, where n represents each of 1 through N, both inclusive. Coupled to the first through the N-th processor input/output information transmission paths and to a system input/output information transmission path for a controlled system, an input/output information path control device connects the system input/output information transmission path to one of the first through the N-th processor input/output information transmission paths.

Abstract: In a computer system comprising first through N-th processors which are provided with first through N-th processor input/output information transmission paths, respectively, an n-th processor is connected to an (n-1)-th processor, an (n-2)-th processor, an (n+1)-th processor, and an (n+2)-th processor, where n represents each of 1 through N, both inclusive. Coupled to the first through the N-th processor input/output information transmission paths and to a system input/output information transmission path for a controlled system, an input/output information path control device connects the system input/output information transmission path to one of the first through the N-th processor input/output information transmission paths.