Patents by Inventor Takahiro Nakatani
Takahiro Nakatani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11948797Abstract: A lower resist (2) is applied on a semiconductor substrate (1). An upper resist (3) is applied on the lower resist (2). A first opening (4) is formed in the upper resist (3) by exposure and development and the lower resist (2) is dissolved with a developer upon the development to form a second opening (5) having a width wider than that of the first opening (4) below the first opening (4) so that a resist pattern (6) in a shape of an eave having an undercut is formed. Baking is performed to thermally shrink the upper resist (3) to bent an eave portion (7) of the upper resist (3) upward. After the baking, a metal film (8) is formed on the resist pattern (6) and on the semiconductor substrate (1) exposed at the second opening (5). The resist pattern (6) and the metal film (8) is removed on the resist pattern (6) and the metal film (8) is left on the semiconductor substrate (1) as an electrode (9).Type: GrantFiled: April 26, 2019Date of Patent: April 2, 2024Assignee: Mitsubishi Electric CorporationInventors: Takahiro Ueno, Masafumi Minami, Mitsunori Nakatani
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Patent number: 11908954Abstract: A semiconductor device includes an insulated gate bipolar transistor region and a diode region adjacent to each other, wherein the insulated gate bipolar transistor region includes base layers of a second conductive type provided on the first main surface side, emitter layers of the first conductive type selectively provided in a surface layer of the base layer on the first main surface side, multiple gate electrodes provided on the first main surface side of the semiconductor substrate, aligned in a first direction extending along the first main surface, and facing the emitter layer, the base layer, and the drift layer via a gate insulating film, carrier injection suppression layers of the first conductive type selectively provided in a surface layer of the base layer on the first main surface side and sandwiched by the base layers in the first direction.Type: GrantFiled: September 23, 2020Date of Patent: February 20, 2024Assignee: Mitsubishi Electric CorporationInventors: Takahiro Nakatani, Tetsuya Nitta, Kakeru Otsuka
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Publication number: 20230126799Abstract: According to the disclosure, a semiconductor device includes a semiconductor substrate including an IGBT region and a diode region, a first electrode provided on an upper surface of the semiconductor substrate and a second electrode provided on a back surface of the semiconductor substrate, wherein the diode region includes an n-type drift layer, a p-type anode layer provided on an upper surface side of the drift layer, and an n-type cathode layer provided on a back surface side of the drift layer, a lifetime control region having crystal defect density higher than crystal defect density of other portions of the drift layer and including protons is provided on a back surface side relative to a center in a thickness direction of the semiconductor substrate among the drift layer, and a maximum value of donor concentration of the lifetime control region is equal to or less than 1.0×1015/cm3.Type: ApplicationFiled: June 9, 2022Publication date: April 27, 2023Applicant: Mitsubishi Electric CorporationInventors: Kosuke SAKAGUCHI, Takahiro NAKATANI, Koichi NISHI, Shinya SONEDA
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Publication number: 20230049223Abstract: According to an aspect of the present disclosure, a semiconductor device includes a substrate including an IGBT region, and a diode region, a surface electrode provided on a top surface of the substrate and a back surface electrode provided on a back surface on an opposite side to the top surface of the substrate, wherein the diode region includes a first portion formed to be thinner than the IGBT region by the top surface of the substrate being recessed, and a second portion provided on one side of the first portion and thicker than the first portion.Type: ApplicationFiled: February 4, 2022Publication date: February 16, 2023Applicant: Mitsubishi Electric CorporationInventors: Hidenori FUJII, Shinya SONEDA, Takahiro NAKATANI
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Patent number: 11569225Abstract: A semiconductor device in which a transistor and a diode are formed on a common semiconductor substrate is provided. The semiconductor substrate includes a transistor region in which a transistor is formed and a diode region in which a diode is formed. At least one first electrode on a second main surface side of the transistor region and at least one second electrode on a second main surface side of the diode region are made of different materials.Type: GrantFiled: March 10, 2021Date of Patent: January 31, 2023Assignee: Mitsubishi Electric CorporationInventors: Shigeto Honda, Takahiro Nakatani, Tetsuya Nitta
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Publication number: 20220173231Abstract: A semiconductor device includes an insulated gate bipolar transistor region having a base layer of a second conductivity type provided in a surface layer of the semiconductor substrate on a first main surface side, an emitter layer of a first conductivity type having an impurity concentration higher than that of a drift layer selectively provided in the surface layer of the base layer on the first main surface side, a plurality of gate electrodes facing the emitter layer, the base layer, and the drift layer via gate insulating films, a counter-doped layer, having an impurity concentration of the second conductivity type higher than that of the base layer and an impurity concentration of the first conductivity type higher than that of the drift layer, and a collector layer of the second conductivity type provided in the surface layer of the semiconductor substrate on a second main surface side.Type: ApplicationFiled: September 3, 2021Publication date: June 2, 2022Applicant: Mitsubishi Electric CorporationInventors: Takahiro NAKATANI, Tetsuya NITTA, Koichi NISHI
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Publication number: 20220122966Abstract: The semiconductor substrate has a first principal surface and a second principal surface. The base contact layer is arranged between the base layer and the first principal surface, and forms a part of the first principal surface. The anode contact region is arranged between the anode layer and the first principal surface, forms a part of the first principal surface, and has a second conductivity type impurity concentration peak value higher than that of the anode layer. The anode contact region includes a first anode contact layer having a lower net concentration and a higher first conductivity type impurity concentration than the base contact layer.Type: ApplicationFiled: August 16, 2021Publication date: April 21, 2022Applicant: Mitsubishi Electric CorporationInventors: Koichi NISHI, Shinya SONEDA, Takahiro NAKATANI
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Patent number: 11222151Abstract: A SEB resistance evaluation method includes: disposing an excitation source within a model of a semiconductor device; and determining an energy of the excitation source at which the semiconductor device exhibits thermal runaway, while varying a voltage applied to the model of the semiconductor device and the energy of the excitation source.Type: GrantFiled: July 20, 2020Date of Patent: January 11, 2022Assignee: Mitsubishi Electric CorporationInventors: Katsumi Uryu, Tadaharu Minato, Takahiro Nakatani
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Publication number: 20210384189Abstract: A semiconductor device in which a transistor and a diode are formed on a common semiconductor substrate is provided. The semiconductor substrate includes a transistor region in which a transistor is formed and a diode region in which a diode is formed. At least one first electrode on a second main surface side of the transistor region and at least one second electrode on a second main surface side of the diode region are made of different materials.Type: ApplicationFiled: March 10, 2021Publication date: December 9, 2021Applicant: Mitsubishi Electric CorporationInventors: Shigeto HONDA, Takahiro NAKATANI, Tetsuya NITTA
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Publication number: 20210305240Abstract: A semiconductor device includes an insulated gate bipolar transistor region and a diode region adjacent to each other, wherein the insulated gate bipolar transistor region includes base layers of a second conductive type provided on the first main surface side, emitter layers of the first conductive type selectively provided in a surface layer of the base layer on the first main surface side, multiple gate electrodes provided on the first main surface side of the semiconductor substrate, aligned in a first direction extending along the first main surface, and facing the emitter layer, the base layer, and the drift layer via a gate insulating film, carrier injection suppression layers of the first conductive type selectively provided in a surface layer of the base layer on the first main surface side and sandwiched by the base layers in the first direction.Type: ApplicationFiled: September 23, 2020Publication date: September 30, 2021Applicant: Mitsubishi Electric CorporationInventors: Takahiro Nakatani, Tetsuya Nitta, Kakeru Otsuka
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Publication number: 20210064796Abstract: A SEB resistance evaluation method includes: disposing an excitation source within a model of a semiconductor device; and determining an energy of the excitation source at which the semiconductor device exhibits thermal runaway, while varying a voltage applied to the model of the semiconductor device and the energy of the excitation source.Type: ApplicationFiled: July 20, 2020Publication date: March 4, 2021Applicant: Mitsubishi Electric CorporationInventors: Katsumi URYU, Tadaharu MINATO, Takahiro NAKATANI
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Patent number: 10866272Abstract: The object is to provide a technique for adjusting a turn-on operation and a turn-off operation of a transistor independently from each other in simulation for evaluating characteristics of the transistor. A simulation circuit for simulation for evaluating characteristics of a transistor includes a gate power supply configured to apply a voltage to a gate terminal of the transistor, a first diode connected between the gate terminal and the gate power supply, and a second diode connected in antiparallel with the first diode.Type: GrantFiled: August 30, 2019Date of Patent: December 15, 2020Assignee: Mitsubishi Electric CorporationInventors: Takahiro Nakatani, Katsumi Uryu, Tadaharu Minato
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Patent number: 10700185Abstract: Trenches each have longer sides extending in a longitudinal direction, and shorter sides linking the longer sides together. The trenches are periodically arranged in the longitudinal direction and a transverse direction. A first region is on a drift layer of a first conductivity type, has a second conductivity type, and is penetrated by the trenches. A second region is on the first region so as to be away from the drift layer, has the first conductivity type, and is in contact with the longer sides of each of the trenches so as to be away from the ends of the longer sides. A third region is on the first region, has the second conductivity type, and has a higher impurity concentration than the first region. The gate electrode is in the trench with a gate insulating film interposed therebetween.Type: GrantFiled: November 6, 2018Date of Patent: June 30, 2020Assignee: Mitsubishi Electric CorporationInventor: Takahiro Nakatani
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Publication number: 20200158774Abstract: The object is to provide a technique for adjusting a turn-on operation and a turn-off operation of a transistor independently from each other in simulation for evaluating characteristics of the transistor. A simulation circuit for simulation for evaluating characteristics of a transistor includes a gate power supply configured to apply a voltage to a gate terminal of the transistor, a first diode connected between the gate terminal and the gate power supply, and a second diode connected in antiparallel with the first diode.Type: ApplicationFiled: August 30, 2019Publication date: May 21, 2020Applicant: Mitsubishi Electric CorporationInventors: Takahiro NAKATANI, Katsumi URYU, Tadaharu MINATO
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Publication number: 20190237567Abstract: Trenches each have longer sides extending in a longitudinal direction, and shorter sides linking the longer sides together. The trenches are periodically arranged in the longitudinal direction and a transverse direction. A first region is on a drift layer of a first conductivity type, has a second conductivity type, and is penetrated by the trenches. A second region is on the first region so as to be away from the drift layer, has the first conductivity type, and is in contact with the longer sides of each of the trenches so as to be away from the ends of the longer sides. A third region is on the first region, has the second conductivity type, and has a higher impurity concentration than the first region. The gate electrode is in the trench with a gate insulating film interposed therebetween.Type: ApplicationFiled: November 6, 2018Publication date: August 1, 2019Applicant: Mitsubishi Electric CorporationInventor: Takahiro NAKATANI
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Patent number: 9059086Abstract: A semiconductor device capable of suppressing generation of a high electric field and preventing a dielectric breakdown from occurring, and a method of manufacturing the same. The method of manufacturing a semiconductor device includes (a) preparing an n+ substrate to be a ground constituted by a silicon carbide semiconductor of a first conductivity type, (b) forming a recess structure surrounding an element region on the n+ substrate by using a resist pattern, and (d) forming a guard ring injection layer to be an impurity layer of a second conductivity type in a recess bottom surface and a recess side surface in the recess structure by impurity injection through the resist pattern, and a corner portion of the recess structure is covered with the impurity layer.Type: GrantFiled: June 9, 2011Date of Patent: June 16, 2015Assignee: Mitsubishi Electric CorporationInventors: Yuji Ebiike, Takahiro Nakatani, Hiroshi Watanabe, Yoshio Fujii, Sunao Aya, Yoshiyuki Nakaki, Tsuyoshi Kawakami, Shuhei Nakata
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Publication number: 20130288467Abstract: A semiconductor device capable of suppressing generation of a high electric field and preventing a dielectric breakdown from occurring, and a method of manufacturing the same. The method of manufacturing a semiconductor device includes (a) preparing an n+ substrate to be a ground constituted by a silicon carbide semiconductor of a first conductivity type, (b) forming a recess structure surrounding an element region on the n+ substrate by using a resist pattern, and (c) forming a guard ring injection layer to be an impurity layer of a second conductivity type in a recess bottom surface and a recess side surface in the recess structure by impurity injection through the resist pattern, and a corner portion of the recess structure is covered with the impurity layer.Type: ApplicationFiled: June 9, 2011Publication date: October 31, 2013Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Yuji Ebiike, Takahiro Nakatani, Hiroshi Watanabe, Yoshio Fujii, Sunao Aya, Yoshiyuki Nakaki, Tsuyoshi Kawakami, Shuhei Nakata